Lines Matching +full:max +full:- +full:link +full:- +full:speed
1 /* SPDX-License-Identifier: GPL-2.0 */
19 #include <linux/io-64-nonatomic-lo-hi.h>
22 /* Code sharing between pci-quirks and xhci hcd */
23 #include "xhci-ext-caps.h"
24 #include "pci-quirks.h"
26 /* max buffer size for trace and debug messages */
32 /* Max number of USB devices for any host controller - limit in section 6.1 */
34 /* Section 5.3.3 - MaxPorts */
44 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
46 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
47 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
48 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
49 * @hcc_params: HCCPARAMS - Capability Parameters
50 * @db_off: DBOFF - Doorbell array offset
51 * @run_regs_off: RTSOFF - Runtime register space offset
63 /* Reserved up to (CAPLENGTH - 0x1C) */
67 /* bits 7:0 - how long is the Capabilities register */
72 /* HCSPARAMS1 - hcs_params1 - bitmasks */
73 /* bits 0:7, Max Device Slots */
76 /* bits 8:18, Max Interrupters */
78 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
81 /* HCSPARAMS2 - hcs_params2 - bitmasks */
85 /* bits 4:7, max number of Event Ring segments */
88 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
92 /* HCSPARAMS3 - hcs_params3 - bitmasks */
93 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
95 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
98 /* HCCPARAMS - hcc_params - bitmasks */
99 /* true: HC can use 64-bit address pointers */
103 /* true: HC uses 64-byte Device Context structures
104 * FIXME 64-byte context structures aren't supported yet.
117 /* true: HC supports Stopped - Short Packet */
121 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
123 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
128 /* db_off bitmask - bits 0:1 reserved */
131 /* run_regs_off bitmask - bits 0:4 reserved */
134 /* HCCPARAMS2 - hcc_params2 - bitmasks */
137 /* true: HC supports Configure endpoint command Max exit latency too large */
159 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
160 * @command: USBCMD - xHC command register
161 * @status: USBSTS - xHC status register
166 * @cmd_ring: CRP - 64-bit Command Ring Pointer
167 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
168 * @config_reg: CONFIG - Configure Register
169 * @port_status_base: PORTSCn - base address for Port Status and Control
172 * register, a Port Link Info register, and a reserved
174 * @port_power_base: PORTPMSCn - base address for
176 * @port_link_base: PORTLIn - base address for Port Link Info (current
177 * Link PM state and control) for USB 2.1 and USB 3.0
188 /* rsvd: offset 0x20-2F */
192 /* rsvd: offset 0x3C-3FF */
199 /* registers for ports 2-255 */
203 /* USBCMD - USB command - command bitmasks */
204 /* start/stop HC execution - do not write unless HC is halted*/
206 /* Reset HC - resets internal HC state machine and all registers (except
211 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
213 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
216 /* light reset (port status stays unchanged) - reset completed when this is 0 */
221 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
223 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
224 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
226 * disabled, or powered-off state.
236 /* IMAN - Interrupt Management Register */
240 /* USBSTS - USB status - status bitmasks */
241 /* HC not running - set to 1 when run/stop bit is cleared. */
245 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
250 /* save state status - '1' means xHC is saving state */
252 /* restore state status - '1' means xHC is restoring state */
258 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
263 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
274 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
278 /* stop ring immediately - abort the currently executing command */
283 /* Command Ring pointer - bit mask for the lower 32 bits. */
286 /* CONFIG - Configure Register - config_reg bitmasks */
287 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
293 /* bits 10:31 - reserved and should be preserved */
295 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
301 /* true: port has an over-current condition */
305 /* Port Link State - bits 5:8
306 * A read gives the current link PM state of the port,
307 * a write with Link State Write Strobe set sets the link state.
326 /* bits 10:13 indicate device speed:
327 * 0 - undefined speed - port hasn't be initialized by a reset yet
328 * 1 - full speed
329 * 2 - low speed
330 * 3 - high speed
331 * 4 - super speed
332 * 5-15 reserved
349 /* Bits 20:23 in the Slot Context are the speed for the device */
360 /* Port Link State Write Strobe - set this when changing link state */
368 * also resets the link, forcing the device through the link training sequence.
372 /* true: over-current change */
374 /* true: reset change - 1 to 0 transition of PORT_RESET */
376 /* port link status change - set on some port link state transitions:
378 * ------------------------------------------------------------------------------
379 * - U3 to Resume Wakeup signaling from a device
380 * - Resume to Recovery to U0 USB 3.0 device resume
381 * - Resume to U0 USB 2.0 device resume
382 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
383 * - U3 to U0 Software resume of USB 2.0 device complete
384 * - U2 to U0 L1 resume of USB 2.1 device complete
385 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
386 * - U0 to disabled L1 entry error with USB 2.1 device
387 * - Any state to inactive Error on USB 3.0 port
390 /* port configure error change - port failed to configure its link partner */
396 /* Cold Attach Status - xHC can set this bit to report device attached during
405 /* wake on over-current (enable) */
408 /* true: device is non-removable - for USB 3.0 roothub emulation */
410 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
413 /* We mark duplicate entries with -1 */
414 #define DUPLICATE_ENTRY ((u8)(-1))
416 /* Port Power Management Status and Control - port_power_base bitmasks */
438 /* USB3 Protocol PORTLI Port Link Information */
464 * to complete link training. usually link trainig completes much faster
471 * struct xhci_intr_reg - Interrupt Register Set
472 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
474 * @irq_control: IMOD - Interrupt Moderation Register.
480 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
499 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
510 /* Counter used to count down the time to the next interrupt - HW use only */
518 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
522 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
531 * MFINDEX - current microframe number
546 * Bits 0 - 7: Endpoint target
547 * Bits 8 - 15: RsvdZ
548 * Bits 16 - 31: Stream ID
565 * @port_info: Port offset, count, and protocol-defined information.
614 * @dev_info: Route string, device speed, hub info, and last valid endpoint
615 * @dev_info2: Max exit latency for device number, root hub port number
619 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
620 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
633 /* Route String - 0:19 */
635 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
639 /* Is this LS/FS device connected through a HS hub? - bit 25 */
641 /* Set if the device is a hub - bit 26 */
643 /* Index of the last valid endpoint context in this device context - 27:31 */
646 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
651 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
662 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
663 * The Slot ID of the hub that isolates the high speed signaling from
664 * this low or full-speed device. '0' if attached to root hub port.
668 * The number of the downstream facing port of the high-speed hub
669 * '0' if the device is not low or full speed.
676 /* USB device address - assigned by the HC */
692 * @ep_info2: information on endpoint type, max packet size, max burst size,
695 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
701 * max payload within an Endpoint Service Interval Time (ESIT).
703 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
704 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
712 /* offset 0x14 - 0x1f reserved for HC internal use */
718 * Endpoint State - bits 0:2
719 * 0 - disabled
720 * 1 - running
721 * 2 - halted due to halt condition - ok to manipulate endpoint ring
722 * 3 - stopped
723 * 4 - TRB error
724 * 5-7 - reserved
732 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
734 /* Mult - Max number of burtst within an interval, in EP companion desc. */
737 /* bits 10:14 are Max Primary Streams */
739 /* Interval - period between requests to an endpoint - 125u increments. */
753 * Force Event - generate transfer events for all TRBs for this endpoint
768 /* bit 7 is Host Initiate Disable - for disabling stream selection */
800 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
802 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
805 * It's useful to pre-allocate these for commands that cannot fail due to
806 * out-of-memory errors, like freeing streams.
830 /* 64-bit stream ring address, cycle state, and stream type */
832 /* offset 0x14 - 0x1f reserved for HC internal use */
836 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
872 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
876 /* ep_interval is zero-based */
878 /* mult and num_packets are one-based */
896 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
925 /* Percentage of bus bandwidth reserved for non-periodic transfers */
953 /* ---- Related to URB cancellation ---- */
989 /* Sorted by max packet size.
990 * Head of the list is the greatest max packet size.
993 /* How many endpoints of each speed are present. */
1036 #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
1038 /* The current max exit latency for the enabled USB3 link states. */
1048 * If a high speed hub is attached to the roothub, each TT associated with that
1069 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
1072 /* 64-bit device addresses; we only write 32-bit addresses */
1077 /* TODO: write function to set the 64-bit device DMA address */
1085 /* 64-bit buffer address, or immediate data */
1099 /* Completion Code - only applicable for some types of TRBs */
1197 return "Stopped - Length Invalid"; in xhci_trb_comp_code_string()
1199 return "Stopped - Short Packet"; in xhci_trb_comp_code_string()
1201 return "Max Exit Latency Too Large Error"; in xhci_trb_comp_code_string()
1220 /* 64-bit segment pointer*/
1239 /* Address device - disable SetAddress */
1242 /* Configure Endpoint - Deconfigure */
1245 /* Stop Ring - Transfer State Preserve */
1277 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1278 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1290 /* Link TRB specific fields */
1294 /* Port ID - bits 31:24 */
1300 /* transfer_len bitmasks - bits 0:16 */
1302 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1307 /* Interrupter Target - which MSI-X vector to target the completion event at */
1314 /* Cycle bit - indicates TRB ownership by HC or HCD */
1352 struct xhci_link_trb link; member
1376 /* Transfer Ring No-op (not for the command ring) */
1405 /* Force Header Command - generate a transaction or link management packet */
1407 /* No-op Command - not for transfer rings */
1409 /* TRB IDs 24-31 reserved */
1423 /* Device Notification Event - device sent function wake notification */
1425 /* MFINDEX Wrap Event - microframe counter wrapped */
1427 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1429 /* Nec vendor-specific command completion event. */
1448 return "Link"; in xhci_trb_type_string()
1452 return "No-Op"; in xhci_trb_type_string()
1482 return "No-Op Command"; in xhci_trb_type_string()
1509 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1520 * since the command ring is 64-byte aligned.
1524 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1525 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1532 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1533 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1541 /* Max packet sized bounce buffer for td-fragmant alignment */
1643 /* 64-bit event ring segment address */
1653 /* xhci->event_ring keeps track of segment dma addresses */
1712 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1732 u32 *psi; /* array of protocol speed ID entries */
1770 /* Cached register copies of read-only HC data */
1789 /* 4KB min, 128MB max */
1793 /* msi-x vectors */
1840 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1843 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1846 * they see this status (any time they drop and re-acquire xhci->lock).
1948 /* platform-specific data -- must come last */
1978 primary_hcd = hcd->primary_hcd; in hcd_to_xhci()
1980 return (struct xhci_hcd *) (primary_hcd->hcd_priv); in hcd_to_xhci()
1985 return xhci->main_hcd; in xhci_to_hcd()
1989 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1991 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1993 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1995 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1997 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
2002 * Some xHCI implementations may support 64-bit address pointers. Registers
2003 * with 64-bit address pointers should be written to with dword accesses by
2005 * xHCI implementations that do not support 64-bit address pointers will ignore
2021 return xhci->quirks & XHCI_LINK_TRB_QUIRK; in xhci_link_trb_quirk()
2225 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, in xhci_urb_to_transfer_ring()
2226 xhci_get_endpoint_index(&urb->ep->desc), in xhci_urb_to_transfer_ring()
2227 urb->stream_id); in xhci_urb_to_transfer_ring()
2231 * struct xhci_vendor_ops - function callbacks for vendor specific operations
2284 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) && in xhci_urb_suitable_for_idt()
2285 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE && in xhci_urb_suitable_for_idt()
2286 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE && in xhci_urb_suitable_for_idt()
2287 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) && in xhci_urb_suitable_for_idt()
2288 !urb->num_sgs) in xhci_urb_suitable_for_idt()
2318 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c", in xhci_decode_trb()
2506 "%s: ctx %08x%08x slot %d speed %d flags %c", in xhci_decode_trb()
2524 "type '%s' -> raw %08x %08x %08x %08x", in xhci_decode_trb()
2565 u32 speed; in xhci_decode_slot_context() local
2570 speed = info & DEV_SPEED; in xhci_decode_slot_context()
2577 switch (speed) { in xhci_decode_slot_context()
2579 s = "full-speed"; in xhci_decode_slot_context()
2582 s = "low-speed"; in xhci_decode_slot_context()
2585 s = "high-speed"; in xhci_decode_slot_context()
2588 s = "super-speed"; in xhci_decode_slot_context()
2591 s = "super-speed plus"; in xhci_decode_slot_context()
2594 s = "UNKNOWN speed"; in xhci_decode_slot_context()
2596 mtt ? " multi-TT" : "", in xhci_decode_slot_context()
2652 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ", in xhci_decode_portsc()
2653 portsc & PORT_POWER ? "Powered" : "Powered-off", in xhci_decode_portsc()
2654 portsc & PORT_CONNECT ? "Connected" : "Not-connected", in xhci_decode_portsc()
2662 ret += sprintf(str + ret, "In-Reset "); in xhci_decode_portsc()
2829 ret = sprintf(str, "State %s mult %d max P. Streams %d %s", in xhci_decode_ep_context()
2833 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ", in xhci_decode_ep_context()