Lines Matching refs:wIndex
487 u16 wIndex, __le32 __iomem *addr, u32 port_status) in xhci_disable_port() argument
506 hcd->self.busnum, wIndex + 1, port_status); in xhci_disable_port()
510 u16 wIndex, __le32 __iomem *addr, u32 port_status) in xhci_clear_port_change_bit() argument
557 wIndex + 1, port_change_bit, port_status); in xhci_clear_port_change_bit()
610 u16 test_mode, u16 wIndex) in xhci_port_set_test_mode() argument
616 port = xhci->usb2_rhub.ports[wIndex]; in xhci_port_set_test_mode()
626 u16 test_mode, u16 wIndex, unsigned long *flags) in xhci_enter_test_mode() argument
663 test_mode, wIndex + 1); in xhci_enter_test_mode()
664 xhci_port_set_test_mode(xhci, test_mode, wIndex); in xhci_enter_test_mode()
806 u16 wIndex) in xhci_del_comp_mod_timer() argument
815 xhci->port_status_u0 |= 1 << wIndex; in xhci_del_comp_mod_timer()
834 u32 wIndex; in xhci_handle_usb2_port_link_resume() local
839 wIndex = port->hcd_portnum; in xhci_handle_usb2_port_link_resume()
846 if (!bus_state->resume_done[wIndex]) { in xhci_handle_usb2_port_link_resume()
848 if (test_bit(wIndex, &bus_state->resuming_ports)) { in xhci_handle_usb2_port_link_resume()
862 set_bit(wIndex, &bus_state->resuming_ports); in xhci_handle_usb2_port_link_resume()
863 bus_state->resume_done[wIndex] = timeout; in xhci_handle_usb2_port_link_resume()
865 usb_hcd_start_port_resume(&hcd->self, wIndex); in xhci_handle_usb2_port_link_resume()
868 } else if (time_after_eq(jiffies, bus_state->resume_done[wIndex])) { in xhci_handle_usb2_port_link_resume()
872 hcd->self.busnum, wIndex + 1); in xhci_handle_usb2_port_link_resume()
874 bus_state->resume_done[wIndex] = 0; in xhci_handle_usb2_port_link_resume()
875 clear_bit(wIndex, &bus_state->resuming_ports); in xhci_handle_usb2_port_link_resume()
877 set_bit(wIndex, &bus_state->rexit_ports); in xhci_handle_usb2_port_link_resume()
884 &bus_state->rexit_done[wIndex], in xhci_handle_usb2_port_link_resume()
890 wIndex + 1); in xhci_handle_usb2_port_link_resume()
901 hcd->self.busnum, wIndex + 1, port_status); in xhci_handle_usb2_port_link_resume()
903 clear_bit(wIndex, &bus_state->rexit_ports); in xhci_handle_usb2_port_link_resume()
906 usb_hcd_end_port_resume(&hcd->self, wIndex); in xhci_handle_usb2_port_link_resume()
907 bus_state->port_c_suspend |= 1 << wIndex; in xhci_handle_usb2_port_link_resume()
908 bus_state->suspended_ports &= ~(1 << wIndex); in xhci_handle_usb2_port_link_resume()
1041 u16 wIndex, u32 raw_port_status, in xhci_get_port_status() argument
1051 port = rhub->ports[wIndex]; in xhci_get_port_status()
1085 if ((bus_state->resume_done[wIndex] || in xhci_get_port_status()
1086 test_bit(wIndex, &bus_state->resuming_ports)) && in xhci_get_port_status()
1089 bus_state->resume_done[wIndex] = 0; in xhci_get_port_status()
1090 clear_bit(wIndex, &bus_state->resuming_ports); in xhci_get_port_status()
1091 usb_hcd_end_port_resume(&hcd->self, wIndex); in xhci_get_port_status()
1094 if (bus_state->port_c_suspend & (1 << wIndex)) in xhci_get_port_status()
1101 u16 wIndex, char *buf, u16 wLength) in xhci_hub_control() argument
1154 if (!wIndex || wIndex > max_ports) in xhci_hub_control()
1156 wIndex--; in xhci_hub_control()
1157 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1163 trace_xhci_get_port_status(wIndex, temp); in xhci_hub_control()
1164 status = xhci_get_port_status(hcd, bus_state, wIndex, temp, in xhci_hub_control()
1170 hcd->self.busnum, wIndex + 1, temp, status); in xhci_hub_control()
1182 port_li = readl(ports[wIndex]->addr + PORTLI); in xhci_hub_control()
1189 link_state = (wIndex & 0xff00) >> 3; in xhci_hub_control()
1191 wake_mask = wIndex & 0xff00; in xhci_hub_control()
1193 test_mode = (wIndex & 0xff00) >> 8; in xhci_hub_control()
1195 timeout = (wIndex & 0xff00) >> 8; in xhci_hub_control()
1196 wIndex &= 0xff; in xhci_hub_control()
1197 if (!wIndex || wIndex > max_ports) in xhci_hub_control()
1199 wIndex--; in xhci_hub_control()
1200 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1210 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1213 xhci_set_link_state(xhci, ports[wIndex], in xhci_hub_control()
1223 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1227 hcd->self.busnum, wIndex + 1); in xhci_hub_control()
1232 wIndex + 1); in xhci_hub_control()
1242 xhci_set_link_state(xhci, ports[wIndex], XDEV_U3); in xhci_hub_control()
1248 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1249 bus_state->suspended_ports |= 1 << wIndex; in xhci_hub_control()
1252 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1256 hcd->self.busnum, wIndex + 1); in xhci_hub_control()
1265 writel(temp | PORT_PE, ports[wIndex]->addr); in xhci_hub_control()
1266 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1273 hcd->self.busnum, wIndex + 1); in xhci_hub_control()
1274 xhci_set_link_state(xhci, ports[wIndex], in xhci_hub_control()
1276 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1306 hcd->self.busnum, wIndex + 1); in xhci_hub_control()
1307 xhci_set_link_state(xhci, ports[wIndex], in xhci_hub_control()
1310 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1321 hcd->self.busnum, wIndex + 1, in xhci_hub_control()
1344 reinit_completion(&bus_state->u3exit_done[wIndex]); in xhci_hub_control()
1347 xhci_set_link_state(xhci, ports[wIndex], in xhci_hub_control()
1355 if (!wait_for_completion_timeout(&bus_state->u3exit_done[wIndex], in xhci_hub_control()
1358 hcd->self.busnum, wIndex + 1); in xhci_hub_control()
1360 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1367 wIndex + 1); in xhci_hub_control()
1376 xhci_set_link_state(xhci, ports[wIndex], USB_SS_PORT_LS_U3); in xhci_hub_control()
1380 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1385 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1386 bus_state->suspended_ports |= 1 << wIndex; in xhci_hub_control()
1396 xhci_set_port_power(xhci, hcd, wIndex, true, &flags); in xhci_hub_control()
1400 writel(temp, ports[wIndex]->addr); in xhci_hub_control()
1402 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1404 hcd->self.busnum, wIndex + 1, temp); in xhci_hub_control()
1407 xhci_set_remote_wake_mask(xhci, ports[wIndex], in xhci_hub_control()
1409 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1411 hcd->self.busnum, wIndex + 1, temp); in xhci_hub_control()
1415 writel(temp, ports[wIndex]->addr); in xhci_hub_control()
1416 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1421 temp = readl(ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1424 writel(temp, ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1429 temp = readl(ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1432 writel(temp, ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1441 retval = xhci_enter_test_mode(xhci, test_mode, wIndex, in xhci_hub_control()
1448 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1451 if (!wIndex || wIndex > max_ports) in xhci_hub_control()
1453 wIndex--; in xhci_hub_control()
1454 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1464 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1473 set_bit(wIndex, &bus_state->resuming_ports); in xhci_hub_control()
1474 usb_hcd_start_port_resume(&hcd->self, wIndex); in xhci_hub_control()
1475 xhci_set_link_state(xhci, ports[wIndex], in xhci_hub_control()
1480 xhci_set_link_state(xhci, ports[wIndex], in xhci_hub_control()
1482 clear_bit(wIndex, &bus_state->resuming_ports); in xhci_hub_control()
1483 usb_hcd_end_port_resume(&hcd->self, wIndex); in xhci_hub_control()
1485 bus_state->port_c_suspend |= 1 << wIndex; in xhci_hub_control()
1488 wIndex + 1); in xhci_hub_control()
1496 bus_state->port_c_suspend &= ~(1 << wIndex); in xhci_hub_control()
1505 xhci_clear_port_change_bit(xhci, wValue, wIndex, in xhci_hub_control()
1506 ports[wIndex]->addr, temp); in xhci_hub_control()
1509 xhci_disable_port(hcd, xhci, wIndex, in xhci_hub_control()
1510 ports[wIndex]->addr, temp); in xhci_hub_control()
1513 xhci_set_port_power(xhci, hcd, wIndex, false, &flags); in xhci_hub_control()