91 #define UHCHR           (0x0064) /* UHC Reset Register */  macro
224 	uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);  in pxa27x_setup_hc()
257 	__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);  in pxa27x_setup_hc()
263 	uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);  in pxa27x_reset_hc()
265 	__raw_writel(uhchr | UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);  in pxa27x_reset_hc()
267 	__raw_writel(uhchr & ~UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);  in pxa27x_reset_hc()
291 	uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) | UHCHR_FSBIR;  in pxa27x_start_hc()
292 	__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);  in pxa27x_start_hc()
294 	while (__raw_readl(pxa_ohci->mmio_base + UHCHR) & UHCHR_FSBIR)  in pxa27x_start_hc()
310 	uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE;  in pxa27x_start_hc()
311 	__raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);  in pxa27x_start_hc()