1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Copyright (c) 2001-2002 by David Brownell
9 /* definitions used for the EHCI driver */
16  * To facilitate the strongest possible byte-order checking from "sparse"
46  * high-speed devices and full/low-speed devices lying behind a TT.
53 	u16			cs_mask;	/* C-mask and S-mask bytes */
66 /* ehci_hcd->lock guards shared data against other CPUs:
92  * ehci-timer.c) in parallel with this list.
188 			the change-suspend feature turned on */
194 	/* per-HC memory pools (could be per-bus, but ...) */
223 	 * 7f2d73788d90 ("usb: ehci: handshake CMD_RUN * instead of STS_HALT")
239 	unsigned		has_ppcd:1; /* support per-port change bits */
264 	/* platform-specific data -- must come last */
271 	return (struct ehci_hcd *) (hcd->hcd_priv);  in hcd_to_ehci()
273 static inline struct usb_hcd *ehci_to_hcd(struct ehci_hcd *ehci)  in ehci_to_hcd()  argument
275 	return container_of((void *) ehci, struct usb_hcd, hcd_priv);  in ehci_to_hcd()
278 /*-------------------------------------------------------------------------*/
280 #include <linux/usb/ehci_def.h>
282 /*-------------------------------------------------------------------------*/
284 #define	QTD_NEXT(ehci, dma)	cpu_to_hc32(ehci, (u32)dma)  argument
287  * EHCI Specification 0.95 Section 3.5
289  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
295 	/* first part defined by EHCI spec */
296 	__hc32			hw_next;	/* see EHCI 3.5.1 */
297 	__hc32			hw_alt_next;    /* see EHCI 3.5.2 */
298 	__hc32			hw_token;       /* see EHCI 3.5.3 */
313 #define ACTIVE_BIT(ehci)	cpu_to_hc32(ehci, QTD_STS_ACTIVE)  argument
314 #define HALT_BIT(ehci)		cpu_to_hc32(ehci, QTD_STS_HALT)  argument
315 #define STATUS_BIT(ehci)	cpu_to_hc32(ehci, QTD_STS_STS)  argument
317 	__hc32			hw_buf[5];        /* see EHCI 3.5.4 */
320 	/* the rest is HCD-private */
327 /* mask NakCnt+T in qh->hw_alt_next */
328 #define QTD_MASK(ehci)	cpu_to_hc32(ehci, ~0x1f)  argument
332 /*-------------------------------------------------------------------------*/
334 /* type tag from {qh,itd,sitd,fstn}->hw_next */
335 #define Q_NEXT_TYPE(ehci, dma)	((dma) & cpu_to_hc32(ehci, 3 << 1))  argument
341  * can be used on one system with SoC EHCI controller using big-endian
342  * descriptors as well as a normal little-endian PCI EHCI controller.
351 #define QH_NEXT(ehci, dma) \  argument
352 		(cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH))
355 #define EHCI_LIST_END(ehci)	cpu_to_hc32(ehci, 1) /* "null pointer" to hw */  argument
374 /*-------------------------------------------------------------------------*/
377  * EHCI Specification 0.95 Section 3.6
379  * See Fig 3-7 "Queue Head Structure Layout".
384 /* first part defined by EHCI spec */
386 	__hc32			hw_next;	/* see EHCI 3.6.1 */
387 	__hc32			hw_info1;       /* see EHCI 3.6.2 */
395 	__hc32			hw_info2;        /* see EHCI 3.6.2 */
401 	__hc32			hw_current;	/* qtd list - see EHCI 3.6.4 */
413 	/* the rest is HCD-private */
445 	unsigned		clearing_tt:1;	/* Clear-TT-Buf in progress */
450 /*-------------------------------------------------------------------------*/
455 	u64			bufp;		/* itd->hw_bufp{,_hi}[pg] |= */
456 	__hc32			transaction;	/* itd->hw_transaction[i] |= */
463  * each packet is one logical usb transaction to the device (not TT),
464  * beginning at stream->next_uframe
474  * ehci_iso_stream - groups all (s)itds for this endpoint.
475  * acts like a qh would, if EHCI had them for ISO.
507 /*-------------------------------------------------------------------------*/
510  * EHCI Specification 0.95 Section 3.3
511  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
516 	/* first part defined by EHCI spec */
517 	__hc32			hw_next;           /* see EHCI 3.3.1 */
518 	__hc32			hw_transaction[8]; /* see EHCI 3.3.2 */
522 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
526 #define ITD_ACTIVE(ehci)	cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)  argument
528 	__hc32			hw_bufp[7];	/* see EHCI 3.3.3 */
531 	/* the rest is HCD-private */
542 	unsigned		index[8];	/* in urb->iso_frame_desc */
545 /*-------------------------------------------------------------------------*/
548  * EHCI Specification 0.95 Section 3.4
549  * siTD, aka split-transaction isochronous Transfer Descriptor
551  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
554 	/* first part defined by EHCI spec */
556 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
557 	__hc32			hw_fullspeed_ep;	/* EHCI table 3-9 */
558 	__hc32			hw_uframe;		/* EHCI table 3-10 */
559 	__hc32			hw_results;		/* EHCI table 3-11 */
571 #define SITD_ACTIVE(ehci)	cpu_to_hc32(ehci, SITD_STS_ACTIVE)  argument
573 	__hc32			hw_buf[2];		/* EHCI table 3-12 */
574 	__hc32			hw_backpointer;		/* EHCI table 3-13 */
577 	/* the rest is HCD-private */
588 /*-------------------------------------------------------------------------*/
591  * EHCI Specification 0.96 Section 3.7
603 	/* the rest is HCD-private */
608 /*-------------------------------------------------------------------------*/
611  * USB-2.0 Specification Sections 11.14 and 11.18
615  * port).  The bandwidth and budgeting information for the full/low-speed bus
616  * below each TT is self-contained and independent of the other TTs or the
617  * high-speed bus.
621  * the best-case estimate of the number of full-speed bytes allocated to an
625  * keep an up-to-date record, we recompute the budget when it is needed.
637 /*-------------------------------------------------------------------------*/
641 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup)	\  argument
642 		ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup)
644 #define ehci_prepare_ports_for_controller_resume(ehci)			\  argument
645 		ehci_adjust_port_wakeup_flags(ehci, false, false)
647 /*-------------------------------------------------------------------------*/
652  * Some EHCI controllers have a Transaction Translator built into the
653  * root hub. This is a non-standard feature.  Each controller will need
658 #define	ehci_is_TDI(e)			(ehci_to_hcd(e)->has_tt)
662 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)  in ehci_port_speed()  argument
664 	if (ehci_is_TDI(ehci)) {  in ehci_port_speed()
665 		switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {  in ehci_port_speed()
682 #define	ehci_port_speed(ehci, portsc)	USB_PORT_STAT_HIGH_SPEED  argument
685 /*-------------------------------------------------------------------------*/
689  * port number in the queue head was 0..N-1 instead of 1..N.
691 #define	ehci_has_fsl_portno_bug(e)		((e)->has_fsl_port_bug)
696 #define PORTSC_FSL_PFSC	24	/* Port Force Full-Speed Connect */
699 /* Some Freescale processors have an erratum (USB A-005275) in which
702 #define ehci_has_fsl_hs_errata(e)	((e)->has_fsl_hs_errata)
708  * Some Freescale/NXP processors have an erratum (USB A-005697)
712 #define ehci_has_fsl_susp_errata(e)	((e)->has_fsl_susp_errata)
715  * While most USB host controllers implement their registers in
716  * little-endian format, a minority (celleb companion chip) implement
725  * as fields of a 32-bit register.
729 #define ehci_big_endian_mmio(e)		((e)->big_endian_mmio)
730 #define ehci_big_endian_capbase(e)	((e)->big_endian_capbase)
737  * Big-endian read/write functions are arch-specific.
745 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,  in ehci_readl()  argument
749 	return ehci_big_endian_mmio(ehci) ?  in ehci_readl()
769 static inline void ehci_writel(const struct ehci_hcd *ehci,  in ehci_writel()  argument
773 	ehci_big_endian_mmio(ehci) ?  in ehci_writel()
777 	if (ehci->imx28_write_fix)  in ehci_writel()
785  * On certain ppc-44x SoC there is a HW issue, that could only worked around with
790 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)  in set_ohci_hcfs()  argument
794 	hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);  in set_ohci_hcfs()
800 	writel_be(hc_control, ehci->ohci_hcctrl_reg);  in set_ohci_hcfs()
801 	(void) readl_be(ehci->ohci_hcctrl_reg);  in set_ohci_hcfs()
804 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)  in set_ohci_hcfs()  argument
808 /*-------------------------------------------------------------------------*/
811  * The AMCC 440EPx not only implements its EHCI registers in big-endian
814  * EHCI controllers accessed through PCI work normally (little-endian
815  * everywhere), so we won't bother supporting a BE-only mode for now.
818 #define ehci_big_endian_desc(e)		((e)->big_endian_desc)
820 /* cpu to ehci */
821 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)  in cpu_to_hc32()  argument
823 	return ehci_big_endian_desc(ehci)  in cpu_to_hc32()
828 /* ehci to cpu */
829 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)  in hc32_to_cpu()  argument
831 	return ehci_big_endian_desc(ehci)  in hc32_to_cpu()
836 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)  in hc32_to_cpup()  argument
838 	return ehci_big_endian_desc(ehci)  in hc32_to_cpup()
845 /* cpu to ehci */
846 static inline __hc32 cpu_to_hc32(const struct ehci_hcd *ehci, const u32 x)  in cpu_to_hc32()  argument
851 /* ehci to cpu */
852 static inline u32 hc32_to_cpu(const struct ehci_hcd *ehci, const __hc32 x)  in hc32_to_cpu()  argument
857 static inline u32 hc32_to_cpup(const struct ehci_hcd *ehci, const __hc32 *x)  in hc32_to_cpup()  argument
864 /*-------------------------------------------------------------------------*/
866 #define ehci_dbg(ehci, fmt, args...) \  argument
867 	dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
868 #define ehci_err(ehci, fmt, args...) \  argument
869 	dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
870 #define ehci_info(ehci, fmt, args...) \  argument
871 	dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
872 #define ehci_warn(ehci, fmt, args...) \  argument
873 	dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
875 /*-------------------------------------------------------------------------*/
877 /* Declarations of things exported for use by ehci platform drivers */
889 extern int	ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
891 extern int	ehci_reset(struct ehci_hcd *ehci);
895 extern void	ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,