Lines Matching +full:big +full:- +full:endian +full:- +full:regs
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2001-2002 by David Brownell
16 * To facilitate the strongest possible byte-order checking from "sparse"
46 * high-speed devices and full/low-speed devices lying behind a TT.
53 u16 cs_mask; /* C-mask and S-mask bytes */
66 /* ehci_hcd->lock guards shared data against other CPUs:
92 * ehci-timer.c) in parallel with this list.
124 struct ehci_regs __iomem *regs; member
188 the change-suspend feature turned on */
194 /* per-HC memory pools (could be per-bus, but ...) */
239 unsigned has_ppcd:1; /* support per-port change bits */
264 /* platform-specific data -- must come last */
271 return (struct ehci_hcd *) (hcd->hcd_priv); in hcd_to_ehci()
278 /*-------------------------------------------------------------------------*/
282 /*-------------------------------------------------------------------------*/
289 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
320 /* the rest is HCD-private */
327 /* mask NakCnt+T in qh->hw_alt_next */
332 /*-------------------------------------------------------------------------*/
334 /* type tag from {qh,itd,sitd,fstn}->hw_next */
341 * can be used on one system with SoC EHCI controller using big-endian
342 * descriptors as well as a normal little-endian PCI EHCI controller.
374 /*-------------------------------------------------------------------------*/
379 * See Fig 3-7 "Queue Head Structure Layout".
401 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
413 /* the rest is HCD-private */
445 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */
450 /*-------------------------------------------------------------------------*/
455 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
456 __hc32 transaction; /* itd->hw_transaction[i] |= */
464 * beginning at stream->next_uframe
474 * ehci_iso_stream - groups all (s)itds for this endpoint.
507 /*-------------------------------------------------------------------------*/
511 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
522 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
531 /* the rest is HCD-private */
542 unsigned index[8]; /* in urb->iso_frame_desc */
545 /*-------------------------------------------------------------------------*/
549 * siTD, aka split-transaction isochronous Transfer Descriptor
551 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
556 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
557 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */
558 __hc32 hw_uframe; /* EHCI table 3-10 */
559 __hc32 hw_results; /* EHCI table 3-11 */
573 __hc32 hw_buf[2]; /* EHCI table 3-12 */
574 __hc32 hw_backpointer; /* EHCI table 3-13 */
577 /* the rest is HCD-private */
588 /*-------------------------------------------------------------------------*/
603 /* the rest is HCD-private */
608 /*-------------------------------------------------------------------------*/
611 * USB-2.0 Specification Sections 11.14 and 11.18
615 * port). The bandwidth and budgeting information for the full/low-speed bus
616 * below each TT is self-contained and independent of the other TTs or the
617 * high-speed bus.
621 * the best-case estimate of the number of full-speed bytes allocated to an
625 * keep an up-to-date record, we recompute the budget when it is needed.
637 /*-------------------------------------------------------------------------*/
647 /*-------------------------------------------------------------------------*/
653 * root hub. This is a non-standard feature. Each controller will need
658 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
665 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { in ehci_port_speed()
685 /*-------------------------------------------------------------------------*/
689 * port number in the queue head was 0..N-1 instead of 1..N.
691 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
696 #define PORTSC_FSL_PFSC 24 /* Port Force Full-Speed Connect */
699 /* Some Freescale processors have an erratum (USB A-005275) in which
702 #define ehci_has_fsl_hs_errata(e) ((e)->has_fsl_hs_errata)
708 * Some Freescale/NXP processors have an erratum (USB A-005697)
712 #define ehci_has_fsl_susp_errata(e) ((e)->has_fsl_susp_errata)
716 * little-endian format, a minority (celleb companion chip) implement
717 * them in big endian format.
725 * as fields of a 32-bit register.
729 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
730 #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
737 * Big-endian read/write functions are arch-specific.
746 __u32 __iomem *regs) in ehci_readl() argument
750 readl_be(regs) : in ehci_readl()
751 readl(regs); in ehci_readl()
753 return readl(regs); in ehci_readl()
770 const unsigned int val, __u32 __iomem *regs) in ehci_writel() argument
774 writel_be(val, regs) : in ehci_writel()
775 writel(val, regs); in ehci_writel()
777 if (ehci->imx28_write_fix) in ehci_writel()
778 imx28_ehci_writel(val, regs); in ehci_writel()
780 writel(val, regs); in ehci_writel()
785 * On certain ppc-44x SoC there is a HW issue, that could only worked around with
794 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); in set_ohci_hcfs()
800 writel_be(hc_control, ehci->ohci_hcctrl_reg); in set_ohci_hcfs()
801 (void) readl_be(ehci->ohci_hcctrl_reg); in set_ohci_hcfs()
808 /*-------------------------------------------------------------------------*/
811 * The AMCC 440EPx not only implements its EHCI registers in big-endian
814 * EHCI controllers accessed through PCI work normally (little-endian
815 * everywhere), so we won't bother supporting a BE-only mode for now.
818 #define ehci_big_endian_desc(e) ((e)->big_endian_desc)
864 /*-------------------------------------------------------------------------*/
867 dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
869 dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
871 dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
873 dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
875 /*-------------------------------------------------------------------------*/