1498 	unsigned char RegValue;  in set_break()  local
1510 	RegValue = read_reg(info, CTL);  in set_break()
1512 		RegValue |= BIT3;  in set_break()
1514 		RegValue &= ~BIT3;  in set_break()
1515 	write_reg(info, CTL, RegValue);  in set_break()
4361   	unsigned char RegValue;  in async_mode()  local
4376 	RegValue = 0x00;  in async_mode()
4378 		RegValue |= BIT1;  in async_mode()
4379 	write_reg(info, MD0, RegValue);  in async_mode()
4390 	RegValue = 0x40;  in async_mode()
4392 	case 7: RegValue |= BIT4 + BIT2; break;  in async_mode()
4393 	case 6: RegValue |= BIT5 + BIT3; break;  in async_mode()
4394 	case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;  in async_mode()
4397 		RegValue |= BIT1;  in async_mode()
4399 			RegValue |= BIT0;  in async_mode()
4401 	write_reg(info, MD1, RegValue);  in async_mode()
4410 	RegValue = 0x00;  in async_mode()
4412 		RegValue |= (BIT1 + BIT0);  in async_mode()
4413 	write_reg(info, MD2, RegValue);  in async_mode()
4421 	RegValue=BIT6;  in async_mode()
4422 	write_reg(info, RXS, RegValue);  in async_mode()
4430 	RegValue=BIT6;  in async_mode()
4431 	write_reg(info, TXS, RegValue);  in async_mode()
4475 	RegValue = 0x10;  in async_mode()
4477 		RegValue |= 0x01;  in async_mode()
4478 	write_reg(info, CTL, RegValue);  in async_mode()
4499 	unsigned char RegValue;  in hdlc_mode()  local
4523 	RegValue = 0x81;  in hdlc_mode()
4525 		RegValue |= BIT4;  in hdlc_mode()
4527 		RegValue |= BIT4;  in hdlc_mode()
4529 		RegValue |= BIT2 + BIT1;  in hdlc_mode()
4530 	write_reg(info, MD0, RegValue);  in hdlc_mode()
4541 	RegValue = 0x00;  in hdlc_mode()
4542 	write_reg(info, MD1, RegValue);  in hdlc_mode()
4554 	RegValue = 0x00;  in hdlc_mode()
4556 	case HDLC_ENCODING_NRZI:	  RegValue |= BIT5; break;  in hdlc_mode()
4557 	case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */  in hdlc_mode()
4558 	case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */  in hdlc_mode()
4559 	case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; 	/* aka Manchester */  in hdlc_mode()
4568 		RegValue |= BIT3;  in hdlc_mode()
4573 		RegValue |= BIT4;  in hdlc_mode()
4575 	write_reg(info, MD2, RegValue);  in hdlc_mode()
4584 	RegValue=0;  in hdlc_mode()
4586 		RegValue |= BIT6;  in hdlc_mode()
4588 		RegValue |= BIT6 + BIT5;  in hdlc_mode()
4589 	write_reg(info, RXS, RegValue);  in hdlc_mode()
4597 	RegValue=0;  in hdlc_mode()
4599 		RegValue |= BIT6;  in hdlc_mode()
4601 		RegValue |= BIT6 + BIT5;  in hdlc_mode()
4602 	write_reg(info, TXS, RegValue);  in hdlc_mode()
4680 	RegValue = 0x10;  in hdlc_mode()
4682 		RegValue |= 0x01;  in hdlc_mode()
4683 	write_reg(info, CTL, RegValue);  in hdlc_mode()
4701 	unsigned char RegValue = 0xff;  in tx_set_idle()  local
4705 	case HDLC_TXIDLE_FLAGS:			RegValue = 0x7e; break;  in tx_set_idle()
4706 	case HDLC_TXIDLE_ALT_ZEROS_ONES:	RegValue = 0xaa; break;  in tx_set_idle()
4707 	case HDLC_TXIDLE_ZEROS:			RegValue = 0x00; break;  in tx_set_idle()
4708 	case HDLC_TXIDLE_ONES:			RegValue = 0xff; break;  in tx_set_idle()
4709 	case HDLC_TXIDLE_ALT_MARK_SPACE:	RegValue = 0xaa; break;  in tx_set_idle()
4710 	case HDLC_TXIDLE_SPACE:			RegValue = 0x00; break;  in tx_set_idle()
4711 	case HDLC_TXIDLE_MARK:			RegValue = 0xff; break;  in tx_set_idle()
4714 	write_reg(info, IDL, RegValue);  in tx_set_idle()
4750 	unsigned char RegValue;  in set_signals()  local
4753 	RegValue = read_reg(info, CTL);  in set_signals()
4755 		RegValue &= ~BIT0;  in set_signals()
4757 		RegValue |= BIT0;  in set_signals()
4758 	write_reg(info, CTL, RegValue);  in set_signals()