401 	wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
403 	wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
408 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
1335 	wr_reg16(info, TCR, value);  in set_break()
2073 	wr_reg16(info, SSR, status); /* clear pending */  in isr_serial()
2213 		wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */  in isr_txeom()
2214 		wr_reg16(info, TCR, val); /* clear reset bit */  in isr_txeom()
2650 			wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);  in rx_enable()
2703 			wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));  in wait_mgsl_event()
2766 			wr_reg16(info, SCR,  in wait_mgsl_event()
2802 	wr_reg16(info, TCR, val);  in set_interface()
3791 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)  in wr_reg16()  function
3843 	wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));  in enable_loopback()
3882 		wr_reg16(info, BDR, (unsigned short)div);  in set_rate()
3892 	wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */  in rx_stop()
3893 	wr_reg16(info, RCR, val);                  /* clear reset bit */  in rx_stop()
3898 	wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);  in rx_stop()
3913 	wr_reg16(info, SSR, IRQ_RXOVER);  in rx_start()
3917 	wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */  in rx_start()
3918 	wr_reg16(info, RCR, val);                  /* clear reset bit */  in rx_start()
3925 		wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));  in rx_start()
3933 		wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));  in rx_start()
3949 	wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));  in rx_start()
3958 		wr_reg16(info, TCR,  in tx_start()
3979 			wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));  in tx_start()
3984 			wr_reg16(info, SSR, IRQ_TXIDLE);  in tx_start()
4003 	wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */  in tx_stop()
4008 	wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));  in tx_stop()
4089 	wr_reg16(info, TCR, val);  in async_mode()
4126 	wr_reg16(info, RCR, val);  in async_mode()
4172 	wr_reg16(info, SCR, val);  in async_mode()
4251 	wr_reg16(info, TCR, val);  in sync_mode()
4314 	wr_reg16(info, RCR, val);  in sync_mode()
4365 		wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));  in sync_mode()
4396 	wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);  in sync_mode()
4423 	wr_reg16(info, TCR, tcr);  in tx_set_idle()
4884 		wr_reg16(info, TIR, patterns[i]);  in register_test()
4885 		wr_reg16(info, BDR, patterns[(i+1)%count]);  in register_test()
4912 	wr_reg16(info, TCR,  in irq_test()
4916 	wr_reg16(info, TDR, 0);  in irq_test()