558 #define MISCSTATUS_TXC_LATCHED		BIT13
579 #define SICR_TXC_ACTIVE			BIT13
581 #define SICR_TXC			(BIT13|BIT12)
1174 		info->cmr_value &= ~BIT13;  in mgsl_isr_receive_status()
1843 	usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));  in shutdown()
4529 				(unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));  in usc_set_sdlc_mode()
4558 			RegValue |= BIT13;  in usc_set_sdlc_mode()
4593 	case HDLC_ENCODING_NRZB:               RegValue |= BIT13; break;  in usc_set_sdlc_mode()
4595 	case HDLC_ENCODING_NRZI_SPACE:	       RegValue |= BIT14 | BIT13; break;  in usc_set_sdlc_mode()
4597 	case HDLC_ENCODING_BIPHASE_SPACE:      RegValue |= BIT15 | BIT13; break;  in usc_set_sdlc_mode()
4599 	case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break;  in usc_set_sdlc_mode()
4665 	case HDLC_ENCODING_NRZB:               RegValue |= BIT13; break;  in usc_set_sdlc_mode()
4667 	case HDLC_ENCODING_NRZI_SPACE:         RegValue |= BIT14 | BIT13; break;  in usc_set_sdlc_mode()
4669 	case HDLC_ENCODING_BIPHASE_SPACE:      RegValue |= BIT15 | BIT13; break;  in usc_set_sdlc_mode()
4671 	case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break;  in usc_set_sdlc_mode()
5241 		usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );  in usc_process_rxoverrun_sync()
5266 		usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );  in usc_process_rxoverrun_sync()
5296 	usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );  in usc_stop_receiver()
5323 	usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );  in usc_start_receiver()
6679 	 	info->cmr_value |= BIT13;  in mgsl_load_tx_dma_buffer()
6814 	usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );  in mgsl_irq_test()
7379  	info->cmr_value &= ~BIT13;  in usc_loopmode_send_done()
7408 	info->cmr_value |= BIT13;  in usc_loopmode_insert_request()