63 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,  in stm32_usart_config_reg_rs485()  argument
70 	*cr3 |= USART_CR3_DEM;  in stm32_usart_config_reg_rs485()
106 	u32 usartdiv, baud, cr1, cr3;  in stm32_usart_config_rs485()  local
117 		cr3 = readl_relaxed(port->membase + ofs->cr3);  in stm32_usart_config_rs485()
127 		stm32_usart_config_reg_rs485(&cr1, &cr3,  in stm32_usart_config_rs485()
133 			cr3 &= ~USART_CR3_DEP;  in stm32_usart_config_rs485()
136 			cr3 |= USART_CR3_DEP;  in stm32_usart_config_rs485()
140 		writel_relaxed(cr3, port->membase + ofs->cr3);  in stm32_usart_config_rs485()
143 		stm32_usart_clr_bits(port, ofs->cr3,  in stm32_usart_config_rs485()
292 	stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);  in stm32_usart_tx_dma_complete()
311 		stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);  in stm32_usart_tx_interrupt_enable()
322 		stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);  in stm32_usart_tx_interrupt_disable()
334 		stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);  in stm32_usart_transmit_chars_pio()
409 	stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);  in stm32_usart_transmit_chars_dma()
430 			stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);  in stm32_usart_transmit_chars()
445 			stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);  in stm32_usart_transmit_chars()
489 		stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);  in stm32_usart_interrupt()
537 		stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE);  in stm32_usart_set_mctrl()
539 		stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE);  in stm32_usart_set_mctrl()
617 		stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);  in stm32_usart_throttle()
632 		stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq);  in stm32_usart_unthrottle()
645 		stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);  in stm32_usart_stop_rx()
755 	u32 cr1, cr2, cr3, isr;  in stm32_usart_set_termios()  local
789 	cr3 = readl_relaxed(port->membase + ofs->cr3);  in stm32_usart_set_termios()
790 	cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE;  in stm32_usart_set_termios()
792 		cr3 &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK);  in stm32_usart_set_termios()
793 		cr3 |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT;  in stm32_usart_set_termios()
794 		cr3 |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT;  in stm32_usart_set_termios()
849 	cr3 |= stm32_port->cr3_irq;  in stm32_usart_set_termios()
857 		cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;  in stm32_usart_set_termios()
909 		cr3 |= USART_CR3_DMAR;  in stm32_usart_set_termios()
912 		stm32_usart_config_reg_rs485(&cr1, &cr3,  in stm32_usart_set_termios()
917 			cr3 &= ~USART_CR3_DEP;  in stm32_usart_set_termios()
920 			cr3 |= USART_CR3_DEP;  in stm32_usart_set_termios()
925 		cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);  in stm32_usart_set_termios()
931 		cr3 &= ~USART_CR3_WUS_MASK;  in stm32_usart_set_termios()
932 		cr3 |= USART_CR3_WUS_START_BIT;  in stm32_usart_set_termios()
935 	writel_relaxed(cr3, port->membase + ofs->cr3);  in stm32_usart_set_termios()
1376 	stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);  in stm32_usart_serial_remove()
1388 	stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);  in stm32_usart_serial_remove()
1525 		stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE);  in stm32_usart_serial_en_wakeup()
1528 		stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);  in stm32_usart_serial_en_wakeup()