63 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,  in stm32_usart_config_reg_rs485()  argument
71 	over8 = *cr1 & USART_CR1_OVER8;  in stm32_usart_config_reg_rs485()
73 	*cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);  in stm32_usart_config_reg_rs485()
85 	*cr1 |= rs485_deat_dedt;  in stm32_usart_config_reg_rs485()
97 	*cr1 |= rs485_deat_dedt;  in stm32_usart_config_reg_rs485()
106 	u32 usartdiv, baud, cr1, cr3;  in stm32_usart_config_rs485()  local
109 	stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));  in stm32_usart_config_rs485()
116 		cr1 = readl_relaxed(port->membase + ofs->cr1);  in stm32_usart_config_rs485()
120 		over8 = cr1 & USART_CR1_OVER8;  in stm32_usart_config_rs485()
127 		stm32_usart_config_reg_rs485(&cr1, &cr3,  in stm32_usart_config_rs485()
141 		writel_relaxed(cr1, port->membase + ofs->cr1);  in stm32_usart_config_rs485()
145 		stm32_usart_clr_bits(port, ofs->cr1,  in stm32_usart_config_rs485()
149 	stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));  in stm32_usart_config_rs485()
313 		stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE);  in stm32_usart_tx_interrupt_enable()
324 		stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);  in stm32_usart_tx_interrupt_disable()
615 	stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);  in stm32_usart_throttle()
630 	stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq);  in stm32_usart_unthrottle()
643 	stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);  in stm32_usart_stop_rx()
675 	stm32_usart_set_bits(port, ofs->cr1, val);  in stm32_usart_startup()
709 	stm32_usart_clr_bits(port, ofs->cr1, val);  in stm32_usart_shutdown()
755 	u32 cr1, cr2, cr3, isr;  in stm32_usart_set_termios()  local
776 	writel_relaxed(0, port->membase + ofs->cr1);  in stm32_usart_set_termios()
783 	cr1 = USART_CR1_TE | USART_CR1_RE;  in stm32_usart_set_termios()
785 		cr1 |= USART_CR1_FIFOEN;  in stm32_usart_set_termios()
805 		cr1 |= USART_CR1_PCE;  in stm32_usart_set_termios()
816 		cr1 |= USART_CR1_M0;  in stm32_usart_set_termios()
818 		cr1 |= USART_CR1_M1;  in stm32_usart_set_termios()
828 			cr1 |= USART_CR1_M0;  in stm32_usart_set_termios()
848 	cr1 |= stm32_port->cr1_irq;  in stm32_usart_set_termios()
852 		cr1 |= USART_CR1_PS;  in stm32_usart_set_termios()
870 		cr1 |= USART_CR1_OVER8;  in stm32_usart_set_termios()
871 		stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8);  in stm32_usart_set_termios()
874 		cr1 &= ~USART_CR1_OVER8;  in stm32_usart_set_termios()
875 		stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8);  in stm32_usart_set_termios()
912 		stm32_usart_config_reg_rs485(&cr1, &cr3,  in stm32_usart_set_termios()
926 		cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);  in stm32_usart_set_termios()
937 	writel_relaxed(cr1, port->membase + ofs->cr1);  in stm32_usart_set_termios()
939 	stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));  in stm32_usart_set_termios()
991 		stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));  in stm32_usart_pm()
1442 	old_cr1 = readl_relaxed(port->membase + ofs->cr1);  in stm32_usart_console_write()
1445 	writel_relaxed(new_cr1, port->membase + ofs->cr1);  in stm32_usart_console_write()
1450 	writel_relaxed(old_cr1, port->membase + ofs->cr1);  in stm32_usart_console_write()
1524 		stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM);  in stm32_usart_serial_en_wakeup()
1527 		stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM);  in stm32_usart_serial_en_wakeup()