495 #define sci_getreg(up, offset)		(&to_sci_port(up)->params->regs[offset])  macro
505 	const struct plat_sci_reg *reg = sci_getreg(p, offset);  in sci_serial_in()
519 	const struct plat_sci_reg *reg = sci_getreg(p, offset);  in sci_serial_out()
745 	} else if (sci_getreg(port, SCSPTR)->size) {  in sci_init_pins()
766 	reg = sci_getreg(port, SCTFDR);  in sci_txfill()
770 	reg = sci_getreg(port, SCFDR);  in sci_txfill()
788 	reg = sci_getreg(port, SCRFDR);  in sci_rxfill()
792 	reg = sci_getreg(port, SCFDR);  in sci_rxfill()
982 	reg = sci_getreg(port, s->params->overrun_reg);  in sci_handle_fifo_overrun()
1040 	if (sci_getreg(port, HSRTRGR)->size) {  in scif_set_rtrg()
1091 	if (sci_getreg(port, HSRTRGR)->size)  in scif_rtrg_enabled()
1553 			(sci_getreg(port, SCxTDR)->offset << port->regshift);  in sci_request_dma_chan()
1557 			(sci_getreg(port, SCxRDR)->offset << port->regshift);  in sci_request_dma_chan()
1823 	else if (sci_getreg(port, s->params->overrun_reg)->size)  in sci_mpxed_interrupt()
2022 	} else if (sci_getreg(port, SCSPTR)->size) {  in sci_set_rts()
2039 	} else if (sci_getreg(port, SCSPTR)->size) {  in sci_get_cts()
2069 		reg = sci_getreg(port, SCFCR);  in sci_set_mctrl()
2141 	if (!sci_getreg(port, SCSPTR)->size) {  in sci_break_ctl()
2355 	reg = sci_getreg(port, SCFCR);  in sci_reset()
2362 	if (sci_getreg(port, SCLSR)->size) {  in sci_reset()
2449 	if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {  in sci_set_termios()
2465 	if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {  in sci_set_termios()
2502 	if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {  in sci_set_termios()
2550 		if (sci_getreg(port, HSSRR)->size) {  in sci_set_termios()
2589 	reg = sci_getreg(port, SCFCR);  in sci_set_termios()