Lines Matching refs:OWL_UART_CTL
26 #define OWL_UART_CTL 0x000 macro
94 ctl = owl_uart_read(port, OWL_UART_CTL); in owl_uart_set_mctrl()
101 owl_uart_write(port, ctl, OWL_UART_CTL); in owl_uart_set_mctrl()
109 ctl = owl_uart_read(port, OWL_UART_CTL); in owl_uart_get_mctrl()
138 val = owl_uart_read(port, OWL_UART_CTL); in owl_uart_stop_rx()
140 owl_uart_write(port, val, OWL_UART_CTL); in owl_uart_stop_rx()
151 val = owl_uart_read(port, OWL_UART_CTL); in owl_uart_stop_tx()
153 owl_uart_write(port, val, OWL_UART_CTL); in owl_uart_stop_tx()
173 val = owl_uart_read(port, OWL_UART_CTL); in owl_uart_start_tx()
175 owl_uart_write(port, val, OWL_UART_CTL); in owl_uart_start_tx()
215 val = owl_uart_read(port, OWL_UART_CTL); in owl_uart_receive_chars()
217 owl_uart_write(port, val, OWL_UART_CTL); in owl_uart_receive_chars()
283 val = owl_uart_read(port, OWL_UART_CTL); in owl_uart_shutdown()
286 owl_uart_write(port, val, OWL_UART_CTL); in owl_uart_shutdown()
311 val = owl_uart_read(port, OWL_UART_CTL); in owl_uart_startup()
314 owl_uart_write(port, val, OWL_UART_CTL); in owl_uart_startup()
338 ctl = owl_uart_read(port, OWL_UART_CTL); in owl_uart_set_termios()
381 owl_uart_write(port, ctl, OWL_UART_CTL); in owl_uart_set_termios()
512 old_ctl = owl_uart_read(port, OWL_UART_CTL); in owl_uart_port_write()
516 owl_uart_write(port, val, OWL_UART_CTL); in owl_uart_port_write()
529 owl_uart_write(port, old_ctl, OWL_UART_CTL); in owl_uart_port_write()