Lines Matching refs:UART_INTR
148 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr) macro
186 unsigned int ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
189 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
203 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
205 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
216 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
218 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
402 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_startup()
404 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_startup()
447 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_shutdown()
695 intr = readl(port->membase + UART_INTR(port)) & in mvebu_uart_console_write()
698 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
708 ctl = intr | readl(port->membase + UART_INTR(port)); in mvebu_uart_console_write()
709 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
784 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port)); in mvebu_uart_suspend()
802 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port)); in mvebu_uart_resume()