186 void msm_write(struct uart_port *port, unsigned int val, unsigned int off)  in msm_write()  function
202 	msm_write(port, 0x06, UART_MREG);  in msm_serial_set_mnd_regs_tcxo()
203 	msm_write(port, 0xF1, UART_NREG);  in msm_serial_set_mnd_regs_tcxo()
204 	msm_write(port, 0x0F, UART_DREG);  in msm_serial_set_mnd_regs_tcxo()
205 	msm_write(port, 0x1A, UART_MNDREG);  in msm_serial_set_mnd_regs_tcxo()
214 	msm_write(port, 0x18, UART_MREG);  in msm_serial_set_mnd_regs_tcxoby4()
215 	msm_write(port, 0xF6, UART_NREG);  in msm_serial_set_mnd_regs_tcxoby4()
216 	msm_write(port, 0x0F, UART_DREG);  in msm_serial_set_mnd_regs_tcxoby4()
217 	msm_write(port, 0x0A, UART_MNDREG);  in msm_serial_set_mnd_regs_tcxoby4()
261 	msm_write(port, val, UARTDM_DMEN);  in msm_stop_dma()
391 	msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);  in msm_wait_for_xmitr()
399 	msm_write(port, msm_port->imr, UART_IMR);  in msm_stop_tx()
412 	msm_write(port, msm_port->imr, UART_IMR);  in msm_start_tx()
418 	msm_write(port, count, UARTDM_NCF_TX);  in msm_reset_dm_count()
446 	msm_write(port, val, UARTDM_DMEN);  in msm_complete_tx_dma()
449 		msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);  in msm_complete_tx_dma()
450 		msm_write(port, UART_CR_TX_ENABLE, UART_CR);  in msm_complete_tx_dma()
462 	msm_write(port, msm_port->imr, UART_IMR);  in msm_complete_tx_dma()
510 	msm_write(port, msm_port->imr, UART_IMR);  in msm_handle_tx_dma()
518 		msm_write(port, val, UARTDM_DMEN);  in msm_handle_tx_dma()
523 		msm_write(port, val, UARTDM_DMEN);  in msm_handle_tx_dma()
550 	msm_write(port, val, UARTDM_DMEN);  in msm_complete_rx_dma()
555 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_complete_rx_dma()
640 	msm_write(uart, msm_port->imr, UART_IMR);  in msm_start_rx_dma()
646 	msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_start_rx_dma()
647 	msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_start_rx_dma()
653 		msm_write(uart, val, UARTDM_DMEN);  in msm_start_rx_dma()
655 	msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);  in msm_start_rx_dma()
658 		msm_write(uart, val, UARTDM_DMEN);  in msm_start_rx_dma()
669 	msm_write(uart, UART_CR_CMD_RESET_RX, UART_CR);  in msm_start_rx_dma()
670 	msm_write(uart, UART_CR_RX_ENABLE, UART_CR);  in msm_start_rx_dma()
672 	msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_start_rx_dma()
673 	msm_write(uart, 0xFFFFFF, UARTDM_DMRX);  in msm_start_rx_dma()
674 	msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_start_rx_dma()
678 	msm_write(uart, msm_port->imr, UART_IMR);  in msm_start_rx_dma()
687 	msm_write(port, msm_port->imr, UART_IMR);  in msm_stop_rx()
698 	msm_write(port, msm_port->imr, UART_IMR);  in msm_enable_ms()
712 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_handle_rx_dm()
769 		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_handle_rx_dm()
770 	msm_write(port, 0xFFFFFF, UARTDM_DMRX);  in msm_handle_rx_dm()
771 	msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_handle_rx_dm()
790 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_handle_rx()
936 	msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);  in msm_handle_delta_cts()
952 	msm_write(port, 0, UART_IMR); /* disable interrupt */  in msm_uart_irq()
956 		msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);  in msm_uart_irq()
962 			msm_write(port, val, UART_CR);  in msm_uart_irq()
964 			msm_write(port, val, UART_CR);  in msm_uart_irq()
981 	msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */  in msm_uart_irq()
1003 	msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);  in msm_reset()
1004 	msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);  in msm_reset()
1005 	msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_reset()
1006 	msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);  in msm_reset()
1007 	msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);  in msm_reset()
1008 	msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);  in msm_reset()
1011 	msm_write(port, mr, UART_MR1);  in msm_reset()
1015 		msm_write(port, 0, UARTDM_DMEN);  in msm_reset()
1026 		msm_write(port, mr, UART_MR1);  in msm_set_mctrl()
1027 		msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);  in msm_set_mctrl()
1030 		msm_write(port, mr, UART_MR1);  in msm_set_mctrl()
1037 		msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);  in msm_break_ctl()
1039 		msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);  in msm_break_ctl()
1136 	msm_write(port, entry->code, UART_CSR);  in msm_set_baud_rate()
1150 	msm_write(port, watermark, UART_IPR);  in msm_set_baud_rate()
1154 	msm_write(port, watermark, UART_RFWR);  in msm_set_baud_rate()
1157 	msm_write(port, 10, UART_TFWR);  in msm_set_baud_rate()
1159 	msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);  in msm_set_baud_rate()
1163 	msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);  in msm_set_baud_rate()
1169 	msm_write(port, msm_port->imr, UART_IMR);  in msm_set_baud_rate()
1172 		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_set_baud_rate()
1173 		msm_write(port, 0xFFFFFF, UARTDM_DMRX);  in msm_set_baud_rate()
1174 		msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_set_baud_rate()
1217 	msm_write(port, data, UART_MR1);  in msm_startup()
1246 	msm_write(port, 0, UART_IMR); /* disable interrupts */  in msm_shutdown()
1313 	msm_write(port, mr, UART_MR2);  in msm_set_termios()
1322 	msm_write(port, mr, UART_MR1);  in msm_set_termios()
1461 			msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);  in msm_poll_get_char_dm()
1465 			msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_poll_get_char_dm()
1466 			msm_write(port, 0xFFFFFF, UARTDM_DMRX);  in msm_poll_get_char_dm()
1467 			msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,  in msm_poll_get_char_dm()
1490 	msm_write(port, 0, UART_IMR);  in msm_poll_get_char()
1498 	msm_write(port, imr, UART_IMR);  in msm_poll_get_char()
1510 	msm_write(port, 0, UART_IMR);  in msm_poll_put_char()
1520 	msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);  in msm_poll_put_char()
1527 	msm_write(port, imr, UART_IMR);  in msm_poll_put_char()