59 #define UART_CR				0x0010  macro
391 	msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);  in msm_wait_for_xmitr()
449 		msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);  in msm_complete_tx_dma()
450 		msm_write(port, UART_CR_TX_ENABLE, UART_CR);  in msm_complete_tx_dma()
555 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_complete_rx_dma()
646 	msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_start_rx_dma()
647 	msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_start_rx_dma()
669 	msm_write(uart, UART_CR_CMD_RESET_RX, UART_CR);  in msm_start_rx_dma()
670 	msm_write(uart, UART_CR_RX_ENABLE, UART_CR);  in msm_start_rx_dma()
672 	msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_start_rx_dma()
674 	msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_start_rx_dma()
712 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_handle_rx_dm()
769 		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_handle_rx_dm()
771 	msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_handle_rx_dm()
790 		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_handle_rx()
936 	msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);  in msm_handle_delta_cts()
956 		msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);  in msm_uart_irq()
962 			msm_write(port, val, UART_CR);  in msm_uart_irq()
964 			msm_write(port, val, UART_CR);  in msm_uart_irq()
1003 	msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);  in msm_reset()
1004 	msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);  in msm_reset()
1005 	msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);  in msm_reset()
1006 	msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);  in msm_reset()
1007 	msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);  in msm_reset()
1008 	msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);  in msm_reset()
1027 		msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);  in msm_set_mctrl()
1037 		msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);  in msm_break_ctl()
1039 		msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);  in msm_break_ctl()
1159 	msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);  in msm_set_baud_rate()
1163 	msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);  in msm_set_baud_rate()
1172 		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_set_baud_rate()
1174 		msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);  in msm_set_baud_rate()
1461 			msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);  in msm_poll_get_char_dm()
1465 			msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);  in msm_poll_get_char_dm()
1468 				  UART_CR);  in msm_poll_get_char_dm()