Lines Matching refs:sport
294 static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) in imx_uart_writel() argument
298 sport->ucr1 = val; in imx_uart_writel()
301 sport->ucr2 = val; in imx_uart_writel()
304 sport->ucr3 = val; in imx_uart_writel()
307 sport->ucr4 = val; in imx_uart_writel()
310 sport->ufcr = val; in imx_uart_writel()
315 writel(val, sport->port.membase + offset); in imx_uart_writel()
318 static u32 imx_uart_readl(struct imx_port *sport, u32 offset) in imx_uart_readl() argument
322 return sport->ucr1; in imx_uart_readl()
331 if (!(sport->ucr2 & UCR2_SRST)) in imx_uart_readl()
332 sport->ucr2 = readl(sport->port.membase + offset); in imx_uart_readl()
333 return sport->ucr2; in imx_uart_readl()
336 return sport->ucr3; in imx_uart_readl()
339 return sport->ucr4; in imx_uart_readl()
342 return sport->ufcr; in imx_uart_readl()
345 return readl(sport->port.membase + offset); in imx_uart_readl()
349 static inline unsigned imx_uart_uts_reg(struct imx_port *sport) in imx_uart_uts_reg() argument
351 return sport->devdata->uts_reg; in imx_uart_uts_reg()
354 static inline int imx_uart_is_imx1(struct imx_port *sport) in imx_uart_is_imx1() argument
356 return sport->devdata->devtype == IMX1_UART; in imx_uart_is_imx1()
359 static inline int imx_uart_is_imx21(struct imx_port *sport) in imx_uart_is_imx21() argument
361 return sport->devdata->devtype == IMX21_UART; in imx_uart_is_imx21()
364 static inline int imx_uart_is_imx53(struct imx_port *sport) in imx_uart_is_imx53() argument
366 return sport->devdata->devtype == IMX53_UART; in imx_uart_is_imx53()
369 static inline int imx_uart_is_imx6q(struct imx_port *sport) in imx_uart_is_imx6q() argument
371 return sport->devdata->devtype == IMX6Q_UART; in imx_uart_is_imx6q()
377 static void imx_uart_ucrs_save(struct imx_port *sport, in imx_uart_ucrs_save() argument
381 ucr->ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_ucrs_save()
382 ucr->ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_ucrs_save()
383 ucr->ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_ucrs_save()
386 static void imx_uart_ucrs_restore(struct imx_port *sport, in imx_uart_ucrs_restore() argument
390 imx_uart_writel(sport, ucr->ucr1, UCR1); in imx_uart_ucrs_restore()
391 imx_uart_writel(sport, ucr->ucr2, UCR2); in imx_uart_ucrs_restore()
392 imx_uart_writel(sport, ucr->ucr3, UCR3); in imx_uart_ucrs_restore()
397 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) in imx_uart_rts_active() argument
401 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS); in imx_uart_rts_active()
405 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) in imx_uart_rts_inactive() argument
410 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS); in imx_uart_rts_inactive()
425 struct imx_port *sport = (struct imx_port *)port; in imx_uart_start_rx() local
428 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_start_rx()
429 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_start_rx()
433 if (sport->dma_is_enabled) { in imx_uart_start_rx()
441 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_start_rx()
442 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_start_rx()
448 struct imx_port *sport = (struct imx_port *)port; in imx_uart_stop_tx() local
451 if (sport->tx_state == OFF) in imx_uart_stop_tx()
458 if (sport->dma_is_txing) in imx_uart_stop_tx()
461 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_stop_tx()
462 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1); in imx_uart_stop_tx()
464 usr2 = imx_uart_readl(sport, USR2); in imx_uart_stop_tx()
470 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_stop_tx()
472 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_stop_tx()
476 if (sport->tx_state == SEND) { in imx_uart_stop_tx()
477 sport->tx_state = WAIT_AFTER_SEND; in imx_uart_stop_tx()
478 start_hrtimer_ms(&sport->trigger_stop_tx, in imx_uart_stop_tx()
483 if (sport->tx_state == WAIT_AFTER_RTS || in imx_uart_stop_tx()
484 sport->tx_state == WAIT_AFTER_SEND) { in imx_uart_stop_tx()
487 hrtimer_try_to_cancel(&sport->trigger_start_tx); in imx_uart_stop_tx()
489 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_stop_tx()
491 imx_uart_rts_active(sport, &ucr2); in imx_uart_stop_tx()
493 imx_uart_rts_inactive(sport, &ucr2); in imx_uart_stop_tx()
494 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_stop_tx()
498 sport->tx_state = OFF; in imx_uart_stop_tx()
501 sport->tx_state = OFF; in imx_uart_stop_tx()
508 struct imx_port *sport = (struct imx_port *)port; in imx_uart_stop_rx() local
511 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_stop_rx()
512 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_stop_rx()
513 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_stop_rx()
515 if (sport->dma_is_enabled) { in imx_uart_stop_rx()
522 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_stop_rx()
523 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_stop_rx()
526 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_stop_rx()
532 struct imx_port *sport = (struct imx_port *)port; in imx_uart_enable_ms() local
534 mod_timer(&sport->timer, jiffies); in imx_uart_enable_ms()
536 mctrl_gpio_enable_ms(sport->gpios); in imx_uart_enable_ms()
539 static void imx_uart_dma_tx(struct imx_port *sport);
542 static inline void imx_uart_transmit_buffer(struct imx_port *sport) in imx_uart_transmit_buffer() argument
544 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_transmit_buffer()
546 if (sport->port.x_char) { in imx_uart_transmit_buffer()
548 imx_uart_writel(sport, sport->port.x_char, URTX0); in imx_uart_transmit_buffer()
549 sport->port.icount.tx++; in imx_uart_transmit_buffer()
550 sport->port.x_char = 0; in imx_uart_transmit_buffer()
554 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { in imx_uart_transmit_buffer()
555 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
559 if (sport->dma_is_enabled) { in imx_uart_transmit_buffer()
565 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_transmit_buffer()
567 if (sport->dma_is_txing) { in imx_uart_transmit_buffer()
569 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_transmit_buffer()
571 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_transmit_buffer()
572 imx_uart_dma_tx(sport); in imx_uart_transmit_buffer()
579 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { in imx_uart_transmit_buffer()
582 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); in imx_uart_transmit_buffer()
584 sport->port.icount.tx++; in imx_uart_transmit_buffer()
588 uart_write_wakeup(&sport->port); in imx_uart_transmit_buffer()
591 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
596 struct imx_port *sport = data; in imx_uart_dma_tx_callback() local
597 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_dma_tx_callback()
598 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx_callback()
602 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
604 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx_callback()
606 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_dma_tx_callback()
608 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_dma_tx_callback()
611 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); in imx_uart_dma_tx_callback()
612 sport->port.icount.tx += sport->tx_bytes; in imx_uart_dma_tx_callback()
614 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); in imx_uart_dma_tx_callback()
616 sport->dma_is_txing = 0; in imx_uart_dma_tx_callback()
619 uart_write_wakeup(&sport->port); in imx_uart_dma_tx_callback()
621 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) in imx_uart_dma_tx_callback()
622 imx_uart_dma_tx(sport); in imx_uart_dma_tx_callback()
623 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { in imx_uart_dma_tx_callback()
624 u32 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_dma_tx_callback()
626 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_dma_tx_callback()
629 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
633 static void imx_uart_dma_tx(struct imx_port *sport) in imx_uart_dma_tx() argument
635 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx()
636 struct scatterlist *sgl = sport->tx_sgl; in imx_uart_dma_tx()
638 struct dma_chan *chan = sport->dma_chan_tx; in imx_uart_dma_tx()
639 struct device *dev = sport->port.dev; in imx_uart_dma_tx()
643 if (sport->dma_is_txing) in imx_uart_dma_tx()
646 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_dma_tx()
648 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_dma_tx()
650 sport->tx_bytes = uart_circ_chars_pending(xmit); in imx_uart_dma_tx()
653 sport->dma_tx_nents = 1; in imx_uart_dma_tx()
654 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); in imx_uart_dma_tx()
656 sport->dma_tx_nents = 2; in imx_uart_dma_tx()
663 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx()
671 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, in imx_uart_dma_tx()
677 desc->callback_param = sport; in imx_uart_dma_tx()
682 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_dma_tx()
684 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_dma_tx()
687 sport->dma_is_txing = 1; in imx_uart_dma_tx()
696 struct imx_port *sport = (struct imx_port *)port; in imx_uart_start_tx() local
699 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) in imx_uart_start_tx()
709 if (sport->tx_state == OFF) { in imx_uart_start_tx()
710 u32 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_start_tx()
712 imx_uart_rts_active(sport, &ucr2); in imx_uart_start_tx()
714 imx_uart_rts_inactive(sport, &ucr2); in imx_uart_start_tx()
715 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_start_tx()
720 sport->tx_state = WAIT_AFTER_RTS; in imx_uart_start_tx()
721 start_hrtimer_ms(&sport->trigger_start_tx, in imx_uart_start_tx()
726 if (sport->tx_state == WAIT_AFTER_SEND in imx_uart_start_tx()
727 || sport->tx_state == WAIT_AFTER_RTS) { in imx_uart_start_tx()
729 hrtimer_try_to_cancel(&sport->trigger_stop_tx); in imx_uart_start_tx()
736 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
737 u32 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_start_tx()
739 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_start_tx()
742 sport->tx_state = SEND; in imx_uart_start_tx()
745 sport->tx_state = SEND; in imx_uart_start_tx()
748 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
749 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_start_tx()
750 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1); in imx_uart_start_tx()
753 if (sport->dma_is_enabled) { in imx_uart_start_tx()
754 if (sport->port.x_char) { in imx_uart_start_tx()
757 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_start_tx()
760 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_start_tx()
766 imx_uart_dma_tx(sport); in imx_uart_start_tx()
773 struct imx_port *sport = dev_id; in __imx_uart_rtsint() local
776 imx_uart_writel(sport, USR1_RTSD, USR1); in __imx_uart_rtsint()
777 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; in __imx_uart_rtsint()
778 uart_handle_cts_change(&sport->port, !!usr1); in __imx_uart_rtsint()
779 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in __imx_uart_rtsint()
786 struct imx_port *sport = dev_id; in imx_uart_rtsint() local
789 spin_lock(&sport->port.lock); in imx_uart_rtsint()
793 spin_unlock(&sport->port.lock); in imx_uart_rtsint()
800 struct imx_port *sport = dev_id; in imx_uart_txint() local
802 spin_lock(&sport->port.lock); in imx_uart_txint()
803 imx_uart_transmit_buffer(sport); in imx_uart_txint()
804 spin_unlock(&sport->port.lock); in imx_uart_txint()
810 struct imx_port *sport = dev_id; in __imx_uart_rxint() local
812 struct tty_port *port = &sport->port.state->port; in __imx_uart_rxint()
814 while (imx_uart_readl(sport, USR2) & USR2_RDR) { in __imx_uart_rxint()
818 sport->port.icount.rx++; in __imx_uart_rxint()
820 rx = imx_uart_readl(sport, URXD0); in __imx_uart_rxint()
822 usr2 = imx_uart_readl(sport, USR2); in __imx_uart_rxint()
824 imx_uart_writel(sport, USR2_BRCD, USR2); in __imx_uart_rxint()
825 if (uart_handle_break(&sport->port)) in __imx_uart_rxint()
829 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) in __imx_uart_rxint()
834 sport->port.icount.brk++; in __imx_uart_rxint()
836 sport->port.icount.parity++; in __imx_uart_rxint()
838 sport->port.icount.frame++; in __imx_uart_rxint()
840 sport->port.icount.overrun++; in __imx_uart_rxint()
842 if (rx & sport->port.ignore_status_mask) { in __imx_uart_rxint()
848 rx &= (sport->port.read_status_mask | 0xFF); in __imx_uart_rxint()
859 sport->port.sysrq = 0; in __imx_uart_rxint()
862 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) in __imx_uart_rxint()
866 sport->port.icount.buf_overrun++; in __imx_uart_rxint()
877 struct imx_port *sport = dev_id; in imx_uart_rxint() local
880 spin_lock(&sport->port.lock); in imx_uart_rxint()
884 spin_unlock(&sport->port.lock); in imx_uart_rxint()
889 static void imx_uart_clear_rx_errors(struct imx_port *sport);
894 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) in imx_uart_get_hwmctrl() argument
897 unsigned usr1 = imx_uart_readl(sport, USR1); in imx_uart_get_hwmctrl()
898 unsigned usr2 = imx_uart_readl(sport, USR2); in imx_uart_get_hwmctrl()
907 if (sport->dte_mode) in imx_uart_get_hwmctrl()
908 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) in imx_uart_get_hwmctrl()
917 static void imx_uart_mctrl_check(struct imx_port *sport) in imx_uart_mctrl_check() argument
921 status = imx_uart_get_hwmctrl(sport); in imx_uart_mctrl_check()
922 changed = status ^ sport->old_status; in imx_uart_mctrl_check()
927 sport->old_status = status; in imx_uart_mctrl_check()
930 sport->port.icount.rng++; in imx_uart_mctrl_check()
932 sport->port.icount.dsr++; in imx_uart_mctrl_check()
934 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); in imx_uart_mctrl_check()
936 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); in imx_uart_mctrl_check()
938 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in imx_uart_mctrl_check()
943 struct imx_port *sport = dev_id; in imx_uart_int() local
953 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_int()
955 usr1 = imx_uart_readl(sport, USR1); in imx_uart_int()
956 usr2 = imx_uart_readl(sport, USR2); in imx_uart_int()
957 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_int()
958 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_int()
959 ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_int()
960 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_int()
988 imx_uart_writel(sport, USR1_AGTIM, USR1); in imx_uart_int()
995 imx_uart_transmit_buffer(sport); in imx_uart_int()
1000 imx_uart_writel(sport, USR1_DTRD, USR1); in imx_uart_int()
1002 imx_uart_mctrl_check(sport); in imx_uart_int()
1013 imx_uart_writel(sport, USR1_AWAKE, USR1); in imx_uart_int()
1018 sport->port.icount.overrun++; in imx_uart_int()
1019 imx_uart_writel(sport, USR2_ORE, USR2); in imx_uart_int()
1023 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_int()
1033 struct imx_port *sport = (struct imx_port *)port; in imx_uart_tx_empty() local
1036 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; in imx_uart_tx_empty()
1039 if (sport->dma_is_txing) in imx_uart_tx_empty()
1048 struct imx_port *sport = (struct imx_port *)port; in imx_uart_get_mctrl() local
1049 unsigned int ret = imx_uart_get_hwmctrl(sport); in imx_uart_get_mctrl()
1051 mctrl_gpio_get(sport->gpios, &ret); in imx_uart_get_mctrl()
1059 struct imx_port *sport = (struct imx_port *)port; in imx_uart_set_mctrl() local
1069 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_set_mctrl()
1081 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_set_mctrl()
1084 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; in imx_uart_set_mctrl()
1087 imx_uart_writel(sport, ucr3, UCR3); in imx_uart_set_mctrl()
1089 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; in imx_uart_set_mctrl()
1092 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); in imx_uart_set_mctrl()
1094 mctrl_gpio_set(sport->gpios, mctrl); in imx_uart_set_mctrl()
1102 struct imx_port *sport = (struct imx_port *)port; in imx_uart_break_ctl() local
1106 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_break_ctl()
1108 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; in imx_uart_break_ctl()
1113 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_break_ctl()
1115 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_break_ctl()
1124 struct imx_port *sport = from_timer(sport, t, timer); in imx_uart_timeout() local
1127 if (sport->port.state) { in imx_uart_timeout()
1128 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_timeout()
1129 imx_uart_mctrl_check(sport); in imx_uart_timeout()
1130 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_timeout()
1132 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); in imx_uart_timeout()
1146 struct imx_port *sport = data; in imx_uart_dma_rx_callback() local
1147 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_dma_rx_callback()
1148 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_dma_rx_callback()
1149 struct tty_port *port = &sport->port.state->port; in imx_uart_dma_rx_callback()
1151 struct circ_buf *rx_ring = &sport->rx_ring; in imx_uart_dma_rx_callback()
1157 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); in imx_uart_dma_rx_callback()
1160 imx_uart_clear_rx_errors(sport); in imx_uart_dma_rx_callback()
1164 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { in imx_uart_dma_rx_callback()
1181 bd_size = sg_dma_len(sgl) / sport->rx_periods; in imx_uart_dma_rx_callback()
1191 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1195 sport->rx_buf + rx_ring->tail, r_bytes); in imx_uart_dma_rx_callback()
1198 dma_sync_sg_for_device(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1202 sport->port.icount.buf_overrun++; in imx_uart_dma_rx_callback()
1204 sport->port.icount.rx += w_bytes; in imx_uart_dma_rx_callback()
1213 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); in imx_uart_dma_rx_callback()
1221 static int imx_uart_start_rx_dma(struct imx_port *sport) in imx_uart_start_rx_dma() argument
1223 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_start_rx_dma()
1224 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_start_rx_dma()
1225 struct device *dev = sport->port.dev; in imx_uart_start_rx_dma()
1229 sport->rx_ring.head = 0; in imx_uart_start_rx_dma()
1230 sport->rx_ring.tail = 0; in imx_uart_start_rx_dma()
1231 sport->rx_periods = RX_DMA_PERIODS; in imx_uart_start_rx_dma()
1233 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); in imx_uart_start_rx_dma()
1241 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, in imx_uart_start_rx_dma()
1250 desc->callback_param = sport; in imx_uart_start_rx_dma()
1253 sport->dma_is_rxing = 1; in imx_uart_start_rx_dma()
1254 sport->rx_cookie = dmaengine_submit(desc); in imx_uart_start_rx_dma()
1259 static void imx_uart_clear_rx_errors(struct imx_port *sport) in imx_uart_clear_rx_errors() argument
1261 struct tty_port *port = &sport->port.state->port; in imx_uart_clear_rx_errors()
1264 usr1 = imx_uart_readl(sport, USR1); in imx_uart_clear_rx_errors()
1265 usr2 = imx_uart_readl(sport, USR2); in imx_uart_clear_rx_errors()
1268 sport->port.icount.brk++; in imx_uart_clear_rx_errors()
1269 imx_uart_writel(sport, USR2_BRCD, USR2); in imx_uart_clear_rx_errors()
1270 uart_handle_break(&sport->port); in imx_uart_clear_rx_errors()
1272 sport->port.icount.buf_overrun++; in imx_uart_clear_rx_errors()
1276 sport->port.icount.frame++; in imx_uart_clear_rx_errors()
1277 imx_uart_writel(sport, USR1_FRAMERR, USR1); in imx_uart_clear_rx_errors()
1279 sport->port.icount.parity++; in imx_uart_clear_rx_errors()
1280 imx_uart_writel(sport, USR1_PARITYERR, USR1); in imx_uart_clear_rx_errors()
1285 sport->port.icount.overrun++; in imx_uart_clear_rx_errors()
1286 imx_uart_writel(sport, USR2_ORE, USR2); in imx_uart_clear_rx_errors()
1296 static void imx_uart_setup_ufcr(struct imx_port *sport, in imx_uart_setup_ufcr() argument
1302 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); in imx_uart_setup_ufcr()
1304 imx_uart_writel(sport, val, UFCR); in imx_uart_setup_ufcr()
1307 static void imx_uart_dma_exit(struct imx_port *sport) in imx_uart_dma_exit() argument
1309 if (sport->dma_chan_rx) { in imx_uart_dma_exit()
1310 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_dma_exit()
1311 dma_release_channel(sport->dma_chan_rx); in imx_uart_dma_exit()
1312 sport->dma_chan_rx = NULL; in imx_uart_dma_exit()
1313 sport->rx_cookie = -EINVAL; in imx_uart_dma_exit()
1314 kfree(sport->rx_buf); in imx_uart_dma_exit()
1315 sport->rx_buf = NULL; in imx_uart_dma_exit()
1318 if (sport->dma_chan_tx) { in imx_uart_dma_exit()
1319 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_dma_exit()
1320 dma_release_channel(sport->dma_chan_tx); in imx_uart_dma_exit()
1321 sport->dma_chan_tx = NULL; in imx_uart_dma_exit()
1325 static int imx_uart_dma_init(struct imx_port *sport) in imx_uart_dma_init() argument
1328 struct device *dev = sport->port.dev; in imx_uart_dma_init()
1332 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); in imx_uart_dma_init()
1333 if (!sport->dma_chan_rx) { in imx_uart_dma_init()
1340 slave_config.src_addr = sport->port.mapbase + URXD0; in imx_uart_dma_init()
1344 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); in imx_uart_dma_init()
1350 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL); in imx_uart_dma_init()
1351 if (!sport->rx_buf) { in imx_uart_dma_init()
1355 sport->rx_ring.buf = sport->rx_buf; in imx_uart_dma_init()
1358 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); in imx_uart_dma_init()
1359 if (!sport->dma_chan_tx) { in imx_uart_dma_init()
1366 slave_config.dst_addr = sport->port.mapbase + URTX0; in imx_uart_dma_init()
1369 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); in imx_uart_dma_init()
1377 imx_uart_dma_exit(sport); in imx_uart_dma_init()
1381 static void imx_uart_enable_dma(struct imx_port *sport) in imx_uart_enable_dma() argument
1385 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); in imx_uart_enable_dma()
1388 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_enable_dma()
1390 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_enable_dma()
1392 sport->dma_is_enabled = 1; in imx_uart_enable_dma()
1395 static void imx_uart_disable_dma(struct imx_port *sport) in imx_uart_disable_dma() argument
1400 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_disable_dma()
1402 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_disable_dma()
1404 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); in imx_uart_disable_dma()
1406 sport->dma_is_enabled = 0; in imx_uart_disable_dma()
1414 struct imx_port *sport = (struct imx_port *)port; in imx_uart_startup() local
1420 retval = clk_prepare_enable(sport->clk_per); in imx_uart_startup()
1423 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_startup()
1425 clk_disable_unprepare(sport->clk_per); in imx_uart_startup()
1429 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); in imx_uart_startup()
1434 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_startup()
1440 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); in imx_uart_startup()
1443 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) in imx_uart_startup()
1446 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_startup()
1450 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_startup()
1452 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_startup()
1454 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_startup()
1460 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); in imx_uart_startup()
1461 imx_uart_writel(sport, USR2_ORE, USR2); in imx_uart_startup()
1463 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; in imx_uart_startup()
1465 if (sport->have_rtscts) in imx_uart_startup()
1468 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_startup()
1470 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR); in imx_uart_startup()
1473 if (sport->inverted_rx) in imx_uart_startup()
1475 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_startup()
1477 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT; in imx_uart_startup()
1481 if (sport->inverted_tx) in imx_uart_startup()
1484 if (!imx_uart_is_imx1(sport)) { in imx_uart_startup()
1487 if (sport->dte_mode) in imx_uart_startup()
1491 imx_uart_writel(sport, ucr3, UCR3); in imx_uart_startup()
1493 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; in imx_uart_startup()
1495 if (!sport->have_rtscts) in imx_uart_startup()
1501 if (!imx_uart_is_imx1(sport)) in imx_uart_startup()
1503 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_startup()
1508 imx_uart_enable_ms(&sport->port); in imx_uart_startup()
1511 imx_uart_enable_dma(sport); in imx_uart_startup()
1512 imx_uart_start_rx_dma(sport); in imx_uart_startup()
1514 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_startup()
1516 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_startup()
1518 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_startup()
1520 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_startup()
1523 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_startup()
1530 struct imx_port *sport = (struct imx_port *)port; in imx_uart_shutdown() local
1534 if (sport->dma_is_enabled) { in imx_uart_shutdown()
1535 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_shutdown()
1536 if (sport->dma_is_txing) { in imx_uart_shutdown()
1537 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], in imx_uart_shutdown()
1538 sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_shutdown()
1539 sport->dma_is_txing = 0; in imx_uart_shutdown()
1541 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_shutdown()
1542 if (sport->dma_is_rxing) { in imx_uart_shutdown()
1543 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, in imx_uart_shutdown()
1545 sport->dma_is_rxing = 0; in imx_uart_shutdown()
1548 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1551 imx_uart_disable_dma(sport); in imx_uart_shutdown()
1552 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1553 imx_uart_dma_exit(sport); in imx_uart_shutdown()
1556 mctrl_gpio_disable_ms(sport->gpios); in imx_uart_shutdown()
1558 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1559 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_shutdown()
1561 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_shutdown()
1562 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1567 del_timer_sync(&sport->timer); in imx_uart_shutdown()
1573 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1575 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_shutdown()
1577 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_shutdown()
1579 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_shutdown()
1581 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_shutdown()
1583 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1585 clk_disable_unprepare(sport->clk_per); in imx_uart_shutdown()
1586 clk_disable_unprepare(sport->clk_ipg); in imx_uart_shutdown()
1592 struct imx_port *sport = (struct imx_port *)port; in imx_uart_flush_buffer() local
1593 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_flush_buffer()
1597 if (!sport->dma_chan_tx) in imx_uart_flush_buffer()
1600 sport->tx_bytes = 0; in imx_uart_flush_buffer()
1601 dmaengine_terminate_all(sport->dma_chan_tx); in imx_uart_flush_buffer()
1602 if (sport->dma_is_txing) { in imx_uart_flush_buffer()
1605 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, in imx_uart_flush_buffer()
1607 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_flush_buffer()
1609 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_flush_buffer()
1610 sport->dma_is_txing = 0; in imx_uart_flush_buffer()
1624 ubir = imx_uart_readl(sport, UBIR); in imx_uart_flush_buffer()
1625 ubmr = imx_uart_readl(sport, UBMR); in imx_uart_flush_buffer()
1626 uts = imx_uart_readl(sport, IMX21_UTS); in imx_uart_flush_buffer()
1628 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_flush_buffer()
1630 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_flush_buffer()
1632 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_flush_buffer()
1636 imx_uart_writel(sport, ubir, UBIR); in imx_uart_flush_buffer()
1637 imx_uart_writel(sport, ubmr, UBMR); in imx_uart_flush_buffer()
1638 imx_uart_writel(sport, uts, IMX21_UTS); in imx_uart_flush_buffer()
1645 struct imx_port *sport = (struct imx_port *)port; in imx_uart_set_termios() local
1664 del_timer_sync(&sport->timer); in imx_uart_set_termios()
1672 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_set_termios()
1678 old_ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_set_termios()
1685 if (!sport->have_rtscts) in imx_uart_set_termios()
1695 imx_uart_rts_active(sport, &ucr2); in imx_uart_set_termios()
1697 imx_uart_rts_inactive(sport, &ucr2); in imx_uart_set_termios()
1718 sport->port.read_status_mask = 0; in imx_uart_set_termios()
1720 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); in imx_uart_set_termios()
1722 sport->port.read_status_mask |= URXD_BRK; in imx_uart_set_termios()
1727 sport->port.ignore_status_mask = 0; in imx_uart_set_termios()
1729 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; in imx_uart_set_termios()
1731 sport->port.ignore_status_mask |= URXD_BRK; in imx_uart_set_termios()
1737 sport->port.ignore_status_mask |= URXD_OVRRUN; in imx_uart_set_termios()
1741 sport->port.ignore_status_mask |= URXD_DUMMY_READ; in imx_uart_set_termios()
1749 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1751 baud = sport->port.uartclk / (quot * 16); in imx_uart_set_termios()
1753 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1759 rational_best_approximation(16 * div * baud, sport->port.uartclk, in imx_uart_set_termios()
1762 tdiv64 = sport->port.uartclk; in imx_uart_set_termios()
1771 ufcr = imx_uart_readl(sport, UFCR); in imx_uart_set_termios()
1773 imx_uart_writel(sport, ufcr, UFCR); in imx_uart_set_termios()
1784 old_ubir = imx_uart_readl(sport, UBIR); in imx_uart_set_termios()
1785 old_ubmr = imx_uart_readl(sport, UBMR); in imx_uart_set_termios()
1787 imx_uart_writel(sport, num, UBIR); in imx_uart_set_termios()
1788 imx_uart_writel(sport, denom, UBMR); in imx_uart_set_termios()
1791 if (!imx_uart_is_imx1(sport)) in imx_uart_set_termios()
1792 imx_uart_writel(sport, sport->port.uartclk / div / 1000, in imx_uart_set_termios()
1795 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_set_termios()
1797 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) in imx_uart_set_termios()
1798 imx_uart_enable_ms(&sport->port); in imx_uart_set_termios()
1800 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_set_termios()
1805 struct imx_port *sport = (struct imx_port *)port; in imx_uart_type() local
1807 return sport->port.type == PORT_IMX ? "IMX" : NULL; in imx_uart_type()
1815 struct imx_port *sport = (struct imx_port *)port; in imx_uart_config_port() local
1818 sport->port.type = PORT_IMX; in imx_uart_config_port()
1829 struct imx_port *sport = (struct imx_port *)port; in imx_uart_verify_port() local
1834 if (sport->port.irq != ser->irq) in imx_uart_verify_port()
1838 if (sport->port.uartclk / 16 != ser->baud_base) in imx_uart_verify_port()
1840 if (sport->port.mapbase != (unsigned long)ser->iomem_base) in imx_uart_verify_port()
1842 if (sport->port.iobase != ser->port) in imx_uart_verify_port()
1853 struct imx_port *sport = (struct imx_port *)port; in imx_uart_poll_init() local
1858 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_poll_init()
1861 retval = clk_prepare_enable(sport->clk_per); in imx_uart_poll_init()
1863 clk_disable_unprepare(sport->clk_ipg); in imx_uart_poll_init()
1865 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); in imx_uart_poll_init()
1867 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_poll_init()
1876 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_poll_init()
1877 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_poll_init()
1879 if (imx_uart_is_imx1(sport)) in imx_uart_poll_init()
1888 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_poll_init()
1889 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_poll_init()
1892 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); in imx_uart_poll_init()
1893 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); in imx_uart_poll_init()
1895 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_poll_init()
1902 struct imx_port *sport = (struct imx_port *)port; in imx_uart_poll_get_char() local
1903 if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) in imx_uart_poll_get_char()
1906 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; in imx_uart_poll_get_char()
1911 struct imx_port *sport = (struct imx_port *)port; in imx_uart_poll_put_char() local
1916 status = imx_uart_readl(sport, USR1); in imx_uart_poll_put_char()
1920 imx_uart_writel(sport, c, URTX0); in imx_uart_poll_put_char()
1924 status = imx_uart_readl(sport, USR2); in imx_uart_poll_put_char()
1933 struct imx_port *sport = (struct imx_port *)port; in imx_uart_rs485_config() local
1937 if (!sport->have_rtscts && !sport->have_rtsgpio) in imx_uart_rs485_config()
1942 if (sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_rs485_config()
1947 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_rs485_config()
1949 imx_uart_rts_active(sport, &ucr2); in imx_uart_rs485_config()
1951 imx_uart_rts_inactive(sport, &ucr2); in imx_uart_rs485_config()
1952 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_rs485_config()
1993 struct imx_port *sport = (struct imx_port *)port; in imx_uart_console_putchar() local
1995 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) in imx_uart_console_putchar()
1998 imx_uart_writel(sport, ch, URTX0); in imx_uart_console_putchar()
2007 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_write() local
2013 if (sport->port.sysrq) in imx_uart_console_write()
2016 locked = spin_trylock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
2018 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
2023 imx_uart_ucrs_save(sport, &old_ucr); in imx_uart_console_write()
2026 if (imx_uart_is_imx1(sport)) in imx_uart_console_write()
2031 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_console_write()
2033 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); in imx_uart_console_write()
2035 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); in imx_uart_console_write()
2041 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); in imx_uart_console_write()
2043 imx_uart_ucrs_restore(sport, &old_ucr); in imx_uart_console_write()
2046 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_console_write()
2054 imx_uart_console_get_options(struct imx_port *sport, int *baud, in imx_uart_console_get_options() argument
2058 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { in imx_uart_console_get_options()
2064 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_console_get_options()
2079 ubir = imx_uart_readl(sport, UBIR) & 0xffff; in imx_uart_console_get_options()
2080 ubmr = imx_uart_readl(sport, UBMR) & 0xffff; in imx_uart_console_get_options()
2082 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; in imx_uart_console_get_options()
2088 uartclk = clk_get_rate(sport->clk_per); in imx_uart_console_get_options()
2107 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", in imx_uart_console_get_options()
2115 struct imx_port *sport; in imx_uart_console_setup() local
2129 sport = imx_uart_ports[co->index]; in imx_uart_console_setup()
2130 if (sport == NULL) in imx_uart_console_setup()
2134 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_console_setup()
2141 imx_uart_console_get_options(sport, &baud, &parity, &bits); in imx_uart_console_setup()
2143 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); in imx_uart_console_setup()
2145 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); in imx_uart_console_setup()
2148 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2152 retval = clk_prepare_enable(sport->clk_per); in imx_uart_console_setup()
2154 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2192 static int imx_uart_probe_dt(struct imx_port *sport, in imx_uart_probe_dt() argument
2198 sport->devdata = of_device_get_match_data(&pdev->dev); in imx_uart_probe_dt()
2199 if (!sport->devdata) in imx_uart_probe_dt()
2208 sport->port.line = ret; in imx_uart_probe_dt()
2212 sport->have_rtscts = 1; in imx_uart_probe_dt()
2215 sport->dte_mode = 1; in imx_uart_probe_dt()
2218 sport->have_rtsgpio = 1; in imx_uart_probe_dt()
2221 sport->inverted_tx = 1; in imx_uart_probe_dt()
2224 sport->inverted_rx = 1; in imx_uart_probe_dt()
2229 static inline int imx_uart_probe_dt(struct imx_port *sport, in imx_uart_probe_dt() argument
2236 static void imx_uart_probe_pdata(struct imx_port *sport, in imx_uart_probe_pdata() argument
2241 sport->port.line = pdev->id; in imx_uart_probe_pdata()
2242 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; in imx_uart_probe_pdata()
2248 sport->have_rtscts = 1; in imx_uart_probe_pdata()
2253 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx); in imx_trigger_start_tx() local
2256 spin_lock_irqsave(&sport->port.lock, flags); in imx_trigger_start_tx()
2257 if (sport->tx_state == WAIT_AFTER_RTS) in imx_trigger_start_tx()
2258 imx_uart_start_tx(&sport->port); in imx_trigger_start_tx()
2259 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_trigger_start_tx()
2266 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx); in imx_trigger_stop_tx() local
2269 spin_lock_irqsave(&sport->port.lock, flags); in imx_trigger_stop_tx()
2270 if (sport->tx_state == WAIT_AFTER_SEND) in imx_trigger_stop_tx()
2271 imx_uart_stop_tx(&sport->port); in imx_trigger_stop_tx()
2272 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_trigger_stop_tx()
2279 struct imx_port *sport; in imx_uart_probe() local
2286 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in imx_uart_probe()
2287 if (!sport) in imx_uart_probe()
2290 ret = imx_uart_probe_dt(sport, pdev); in imx_uart_probe()
2292 imx_uart_probe_pdata(sport, pdev); in imx_uart_probe()
2296 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { in imx_uart_probe()
2298 sport->port.line); in imx_uart_probe()
2313 sport->port.dev = &pdev->dev; in imx_uart_probe()
2314 sport->port.mapbase = res->start; in imx_uart_probe()
2315 sport->port.membase = base; in imx_uart_probe()
2316 sport->port.type = PORT_IMX, in imx_uart_probe()
2317 sport->port.iotype = UPIO_MEM; in imx_uart_probe()
2318 sport->port.irq = rxirq; in imx_uart_probe()
2319 sport->port.fifosize = 32; in imx_uart_probe()
2320 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); in imx_uart_probe()
2321 sport->port.ops = &imx_uart_pops; in imx_uart_probe()
2322 sport->port.rs485_config = imx_uart_rs485_config; in imx_uart_probe()
2323 sport->port.flags = UPF_BOOT_AUTOCONF; in imx_uart_probe()
2324 timer_setup(&sport->timer, imx_uart_timeout, 0); in imx_uart_probe()
2326 sport->gpios = mctrl_gpio_init(&sport->port, 0); in imx_uart_probe()
2327 if (IS_ERR(sport->gpios)) in imx_uart_probe()
2328 return PTR_ERR(sport->gpios); in imx_uart_probe()
2330 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in imx_uart_probe()
2331 if (IS_ERR(sport->clk_ipg)) { in imx_uart_probe()
2332 ret = PTR_ERR(sport->clk_ipg); in imx_uart_probe()
2337 sport->clk_per = devm_clk_get(&pdev->dev, "per"); in imx_uart_probe()
2338 if (IS_ERR(sport->clk_per)) { in imx_uart_probe()
2339 ret = PTR_ERR(sport->clk_per); in imx_uart_probe()
2344 sport->port.uartclk = clk_get_rate(sport->clk_per); in imx_uart_probe()
2347 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_probe()
2354 sport->ucr1 = readl(sport->port.membase + UCR1); in imx_uart_probe()
2355 sport->ucr2 = readl(sport->port.membase + UCR2); in imx_uart_probe()
2356 sport->ucr3 = readl(sport->port.membase + UCR3); in imx_uart_probe()
2357 sport->ucr4 = readl(sport->port.membase + UCR4); in imx_uart_probe()
2358 sport->ufcr = readl(sport->port.membase + UFCR); in imx_uart_probe()
2360 ret = uart_get_rs485_mode(&sport->port); in imx_uart_probe()
2362 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2366 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2367 (!sport->have_rtscts && !sport->have_rtsgpio)) in imx_uart_probe()
2375 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2376 sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_probe()
2377 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && in imx_uart_probe()
2378 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) in imx_uart_probe()
2383 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_probe()
2385 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_probe()
2387 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { in imx_uart_probe()
2394 u32 ufcr = imx_uart_readl(sport, UFCR); in imx_uart_probe()
2396 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); in imx_uart_probe()
2403 imx_uart_writel(sport, in imx_uart_probe()
2409 u32 ufcr = imx_uart_readl(sport, UFCR); in imx_uart_probe()
2411 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); in imx_uart_probe()
2413 if (!imx_uart_is_imx1(sport)) in imx_uart_probe()
2415 imx_uart_writel(sport, ucr3, UCR3); in imx_uart_probe()
2418 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2420 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2421 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2422 sport->trigger_start_tx.function = imx_trigger_start_tx; in imx_uart_probe()
2423 sport->trigger_stop_tx.function = imx_trigger_stop_tx; in imx_uart_probe()
2431 dev_name(&pdev->dev), sport); in imx_uart_probe()
2439 dev_name(&pdev->dev), sport); in imx_uart_probe()
2447 dev_name(&pdev->dev), sport); in imx_uart_probe()
2455 dev_name(&pdev->dev), sport); in imx_uart_probe()
2462 imx_uart_ports[sport->port.line] = sport; in imx_uart_probe()
2464 platform_set_drvdata(pdev, sport); in imx_uart_probe()
2466 return uart_add_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_probe()
2471 struct imx_port *sport = platform_get_drvdata(pdev); in imx_uart_remove() local
2473 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_remove()
2476 static void imx_uart_restore_context(struct imx_port *sport) in imx_uart_restore_context() argument
2480 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_restore_context()
2481 if (!sport->context_saved) { in imx_uart_restore_context()
2482 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_restore_context()
2486 imx_uart_writel(sport, sport->saved_reg[4], UFCR); in imx_uart_restore_context()
2487 imx_uart_writel(sport, sport->saved_reg[5], UESC); in imx_uart_restore_context()
2488 imx_uart_writel(sport, sport->saved_reg[6], UTIM); in imx_uart_restore_context()
2489 imx_uart_writel(sport, sport->saved_reg[7], UBIR); in imx_uart_restore_context()
2490 imx_uart_writel(sport, sport->saved_reg[8], UBMR); in imx_uart_restore_context()
2491 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); in imx_uart_restore_context()
2492 imx_uart_writel(sport, sport->saved_reg[0], UCR1); in imx_uart_restore_context()
2493 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); in imx_uart_restore_context()
2494 imx_uart_writel(sport, sport->saved_reg[2], UCR3); in imx_uart_restore_context()
2495 imx_uart_writel(sport, sport->saved_reg[3], UCR4); in imx_uart_restore_context()
2496 sport->context_saved = false; in imx_uart_restore_context()
2497 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_restore_context()
2500 static void imx_uart_save_context(struct imx_port *sport) in imx_uart_save_context() argument
2505 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_save_context()
2506 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); in imx_uart_save_context()
2507 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); in imx_uart_save_context()
2508 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); in imx_uart_save_context()
2509 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); in imx_uart_save_context()
2510 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); in imx_uart_save_context()
2511 sport->saved_reg[5] = imx_uart_readl(sport, UESC); in imx_uart_save_context()
2512 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); in imx_uart_save_context()
2513 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); in imx_uart_save_context()
2514 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); in imx_uart_save_context()
2515 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); in imx_uart_save_context()
2516 sport->context_saved = true; in imx_uart_save_context()
2517 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_save_context()
2520 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) in imx_uart_enable_wakeup() argument
2524 ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_enable_wakeup()
2526 imx_uart_writel(sport, USR1_AWAKE, USR1); in imx_uart_enable_wakeup()
2531 imx_uart_writel(sport, ucr3, UCR3); in imx_uart_enable_wakeup()
2533 if (sport->have_rtscts) { in imx_uart_enable_wakeup()
2534 u32 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_enable_wakeup()
2539 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_enable_wakeup()
2545 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_suspend_noirq() local
2547 imx_uart_save_context(sport); in imx_uart_suspend_noirq()
2549 clk_disable(sport->clk_ipg); in imx_uart_suspend_noirq()
2558 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_resume_noirq() local
2563 ret = clk_enable(sport->clk_ipg); in imx_uart_resume_noirq()
2567 imx_uart_restore_context(sport); in imx_uart_resume_noirq()
2574 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_suspend() local
2577 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_suspend()
2578 disable_irq(sport->port.irq); in imx_uart_suspend()
2580 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_suspend()
2585 imx_uart_enable_wakeup(sport, true); in imx_uart_suspend()
2592 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_resume() local
2595 imx_uart_enable_wakeup(sport, false); in imx_uart_resume()
2597 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_resume()
2598 enable_irq(sport->port.irq); in imx_uart_resume()
2600 clk_disable_unprepare(sport->clk_ipg); in imx_uart_resume()
2607 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_freeze() local
2609 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_freeze()
2611 return clk_prepare_enable(sport->clk_ipg); in imx_uart_freeze()
2616 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_thaw() local
2618 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_thaw()
2620 clk_disable_unprepare(sport->clk_ipg); in imx_uart_thaw()