Lines Matching +full:auto +full:- +full:baud
1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
10 #include <linux/dma-mapping.h>
23 /* All registers are 8-bit width */
112 /* 32-bit register definition */
225 #define DRIVER_NAME "fsl-lpuart"
302 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
303 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
304 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, },
305 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, },
306 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, },
316 return (sport->devtype == LS1021A_LPUART || in is_layerscape_lpuart()
317 sport->devtype == LS1028A_LPUART); in is_layerscape_lpuart()
322 return sport->devtype == IMX8QXP_LPUART; in is_imx8qxp_lpuart()
327 switch (port->iotype) { in lpuart32_read()
329 return readl(port->membase + off); in lpuart32_read()
331 return ioread32be(port->membase + off); in lpuart32_read()
340 switch (port->iotype) { in lpuart32_write()
342 writel(val, port->membase + off); in lpuart32_write()
345 iowrite32be(val, port->membase + off); in lpuart32_write()
355 ret = clk_prepare_enable(sport->ipg_clk); in __lpuart_enable_clks()
359 ret = clk_prepare_enable(sport->baud_clk); in __lpuart_enable_clks()
361 clk_disable_unprepare(sport->ipg_clk); in __lpuart_enable_clks()
365 clk_disable_unprepare(sport->baud_clk); in __lpuart_enable_clks()
366 clk_disable_unprepare(sport->ipg_clk); in __lpuart_enable_clks()
375 return clk_get_rate(sport->baud_clk); in lpuart_get_baud_clk_rate()
377 return clk_get_rate(sport->ipg_clk); in lpuart_get_baud_clk_rate()
387 temp = readb(port->membase + UARTCR2); in lpuart_stop_tx()
389 writeb(temp, port->membase + UARTCR2); in lpuart_stop_tx()
405 temp = readb(port->membase + UARTCR2); in lpuart_stop_rx()
406 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); in lpuart_stop_rx()
419 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart_dma_tx()
420 struct scatterlist *sgl = sport->tx_sgl; in lpuart_dma_tx()
421 struct device *dev = sport->port.dev; in lpuart_dma_tx()
422 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_dma_tx()
425 if (sport->dma_tx_in_progress) in lpuart_dma_tx()
428 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); in lpuart_dma_tx()
430 if (xmit->tail < xmit->head || xmit->head == 0) { in lpuart_dma_tx()
431 sport->dma_tx_nents = 1; in lpuart_dma_tx()
432 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); in lpuart_dma_tx()
434 sport->dma_tx_nents = 2; in lpuart_dma_tx()
436 sg_set_buf(sgl, xmit->buf + xmit->tail, in lpuart_dma_tx()
437 UART_XMIT_SIZE - xmit->tail); in lpuart_dma_tx()
438 sg_set_buf(sgl + 1, xmit->buf, xmit->head); in lpuart_dma_tx()
441 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx()
448 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, in lpuart_dma_tx()
451 if (!sport->dma_tx_desc) { in lpuart_dma_tx()
452 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx()
458 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; in lpuart_dma_tx()
459 sport->dma_tx_desc->callback_param = sport; in lpuart_dma_tx()
460 sport->dma_tx_in_progress = true; in lpuart_dma_tx()
461 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); in lpuart_dma_tx()
467 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port); in lpuart_stopped_or_empty()
473 struct scatterlist *sgl = &sport->tx_sgl[0]; in lpuart_dma_tx_complete()
474 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart_dma_tx_complete()
475 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_dma_tx_complete()
478 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_dma_tx_complete()
480 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx_complete()
483 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); in lpuart_dma_tx_complete()
485 sport->port.icount.tx += sport->dma_tx_bytes; in lpuart_dma_tx_complete()
486 sport->dma_tx_in_progress = false; in lpuart_dma_tx_complete()
487 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_dma_tx_complete()
490 uart_write_wakeup(&sport->port); in lpuart_dma_tx_complete()
492 if (waitqueue_active(&sport->dma_wait)) { in lpuart_dma_tx_complete()
493 wake_up(&sport->dma_wait); in lpuart_dma_tx_complete()
497 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_dma_tx_complete()
499 if (!lpuart_stopped_or_empty(&sport->port)) in lpuart_dma_tx_complete()
502 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_dma_tx_complete()
507 switch (sport->port.iotype) { in lpuart_dma_datareg_addr()
509 return sport->port.mapbase + UARTDATA; in lpuart_dma_datareg_addr()
511 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; in lpuart_dma_datareg_addr()
513 return sport->port.mapbase + UARTDR; in lpuart_dma_datareg_addr()
527 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); in lpuart_dma_tx_request()
530 dev_err(sport->port.dev, in lpuart_dma_tx_request()
540 return sport->port.iotype == UPIO_MEM32 || in lpuart_is_32()
541 sport->port.iotype == UPIO_MEM32BE; in lpuart_is_32()
547 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_flush_buffer()
550 if (sport->lpuart_dma_tx_use) { in lpuart_flush_buffer()
551 if (sport->dma_tx_in_progress) { in lpuart_flush_buffer()
552 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], in lpuart_flush_buffer()
553 sport->dma_tx_nents, DMA_TO_DEVICE); in lpuart_flush_buffer()
554 sport->dma_tx_in_progress = false; in lpuart_flush_buffer()
560 val = lpuart32_read(&sport->port, UARTFIFO); in lpuart_flush_buffer()
562 lpuart32_write(&sport->port, val, UARTFIFO); in lpuart_flush_buffer()
564 val = readb(sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
566 writeb(val, sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
573 while (!(readb(port->membase + offset) & bit)) in lpuart_wait_bit_set()
593 sport->port.fifosize = 0; in lpuart_poll_init()
595 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_poll_init()
597 writeb(0, sport->port.membase + UARTCR2); in lpuart_poll_init()
599 temp = readb(sport->port.membase + UARTPFIFO); in lpuart_poll_init()
602 sport->port.membase + UARTPFIFO); in lpuart_poll_init()
606 sport->port.membase + UARTCFIFO); in lpuart_poll_init()
609 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_poll_init()
610 readb(sport->port.membase + UARTDR); in lpuart_poll_init()
611 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); in lpuart_poll_init()
614 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_poll_init()
615 writeb(1, sport->port.membase + UARTRWFIFO); in lpuart_poll_init()
618 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); in lpuart_poll_init()
619 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_poll_init()
628 writeb(c, port->membase + UARTDR); in lpuart_poll_put_char()
633 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) in lpuart_poll_get_char()
636 return readb(port->membase + UARTDR); in lpuart_poll_get_char()
645 sport->port.fifosize = 0; in lpuart32_poll_init()
647 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_poll_init()
650 lpuart32_write(&sport->port, 0, UARTCTRL); in lpuart32_poll_init()
652 temp = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_poll_init()
655 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); in lpuart32_poll_init()
658 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); in lpuart32_poll_init()
661 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { in lpuart32_poll_init()
662 lpuart32_read(&sport->port, UARTDATA); in lpuart32_poll_init()
663 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO); in lpuart32_poll_init()
667 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); in lpuart32_poll_init()
668 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_poll_init()
690 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart_transmit_buffer()
692 if (sport->port.x_char) { in lpuart_transmit_buffer()
693 writeb(sport->port.x_char, sport->port.membase + UARTDR); in lpuart_transmit_buffer()
694 sport->port.icount.tx++; in lpuart_transmit_buffer()
695 sport->port.x_char = 0; in lpuart_transmit_buffer()
699 if (lpuart_stopped_or_empty(&sport->port)) { in lpuart_transmit_buffer()
700 lpuart_stop_tx(&sport->port); in lpuart_transmit_buffer()
705 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { in lpuart_transmit_buffer()
706 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); in lpuart_transmit_buffer()
707 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in lpuart_transmit_buffer()
708 sport->port.icount.tx++; in lpuart_transmit_buffer()
712 uart_write_wakeup(&sport->port); in lpuart_transmit_buffer()
715 lpuart_stop_tx(&sport->port); in lpuart_transmit_buffer()
720 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart32_transmit_buffer()
723 if (sport->port.x_char) { in lpuart32_transmit_buffer()
724 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); in lpuart32_transmit_buffer()
725 sport->port.icount.tx++; in lpuart32_transmit_buffer()
726 sport->port.x_char = 0; in lpuart32_transmit_buffer()
730 if (lpuart_stopped_or_empty(&sport->port)) { in lpuart32_transmit_buffer()
731 lpuart32_stop_tx(&sport->port); in lpuart32_transmit_buffer()
735 txcnt = lpuart32_read(&sport->port, UARTWATER); in lpuart32_transmit_buffer()
738 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { in lpuart32_transmit_buffer()
739 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); in lpuart32_transmit_buffer()
740 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in lpuart32_transmit_buffer()
741 sport->port.icount.tx++; in lpuart32_transmit_buffer()
742 txcnt = lpuart32_read(&sport->port, UARTWATER); in lpuart32_transmit_buffer()
748 uart_write_wakeup(&sport->port); in lpuart32_transmit_buffer()
751 lpuart32_stop_tx(&sport->port); in lpuart32_transmit_buffer()
760 temp = readb(port->membase + UARTCR2); in lpuart_start_tx()
761 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); in lpuart_start_tx()
763 if (sport->lpuart_dma_tx_use) { in lpuart_start_tx()
767 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) in lpuart_start_tx()
777 if (sport->lpuart_dma_tx_use) { in lpuart32_start_tx()
794 unsigned char sr1 = readb(port->membase + UARTSR1); in lpuart_tx_empty()
795 unsigned char sfifo = readb(port->membase + UARTSFIFO); in lpuart_tx_empty()
797 if (sport->dma_tx_in_progress) in lpuart_tx_empty()
813 if (sport->dma_tx_in_progress) in lpuart32_tx_empty()
826 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_txint()
828 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_txint()
834 struct tty_port *port = &sport->port.state->port; in lpuart_rxint()
838 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_rxint()
840 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { in lpuart_rxint()
842 sport->port.icount.rx++; in lpuart_rxint()
847 sr = readb(sport->port.membase + UARTSR1); in lpuart_rxint()
848 rx = readb(sport->port.membase + UARTDR); in lpuart_rxint()
850 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) in lpuart_rxint()
855 sport->port.icount.parity++; in lpuart_rxint()
857 sport->port.icount.frame++; in lpuart_rxint()
862 if (sr & sport->port.ignore_status_mask) { in lpuart_rxint()
868 sr &= sport->port.read_status_mask; in lpuart_rxint()
878 sport->port.sysrq = 0; in lpuart_rxint()
886 sport->port.icount.overrun += overrun; in lpuart_rxint()
892 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_rxint()
893 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); in lpuart_rxint()
896 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_rxint()
905 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_txint()
907 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_txint()
913 struct tty_port *port = &sport->port.state->port; in lpuart32_rxint()
917 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_rxint()
919 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { in lpuart32_rxint()
921 sport->port.icount.rx++; in lpuart32_rxint()
926 sr = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_rxint()
927 rx = lpuart32_read(&sport->port, UARTDATA); in lpuart32_rxint()
930 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) in lpuart32_rxint()
935 sport->port.icount.parity++; in lpuart32_rxint()
937 sport->port.icount.frame++; in lpuart32_rxint()
940 sport->port.icount.overrun++; in lpuart32_rxint()
942 if (sr & sport->port.ignore_status_mask) { in lpuart32_rxint()
948 sr &= sport->port.read_status_mask; in lpuart32_rxint()
958 sport->port.sysrq = 0; in lpuart32_rxint()
965 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_rxint()
975 sts = readb(sport->port.membase + UARTSR1); in lpuart_int()
978 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { in lpuart_int()
979 readb(sport->port.membase + UARTDR); in lpuart_int()
980 uart_handle_break(&sport->port); in lpuart_int()
982 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_int()
986 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) in lpuart_int()
989 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) in lpuart_int()
1000 sts = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_int()
1001 rxcount = lpuart32_read(&sport->port, UARTWATER); in lpuart32_int()
1004 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) in lpuart32_int()
1007 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) in lpuart32_int()
1010 lpuart32_write(&sport->port, sts, UARTSTAT); in lpuart32_int()
1018 while (count--) { in lpuart_handle_sysrq_chars()
1027 struct circ_buf *ring = &sport->rx_ring; in lpuart_handle_sysrq()
1030 if (ring->head < ring->tail) { in lpuart_handle_sysrq()
1031 count = sport->rx_sgl.length - ring->tail; in lpuart_handle_sysrq()
1032 lpuart_handle_sysrq_chars(&sport->port, in lpuart_handle_sysrq()
1033 ring->buf + ring->tail, count); in lpuart_handle_sysrq()
1034 ring->tail = 0; in lpuart_handle_sysrq()
1037 if (ring->head > ring->tail) { in lpuart_handle_sysrq()
1038 count = ring->head - ring->tail; in lpuart_handle_sysrq()
1039 lpuart_handle_sysrq_chars(&sport->port, in lpuart_handle_sysrq()
1040 ring->buf + ring->tail, count); in lpuart_handle_sysrq()
1041 ring->tail = ring->head; in lpuart_handle_sysrq()
1047 struct tty_port *port = &sport->port.state->port; in lpuart_copy_rx_to_tty()
1050 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_copy_rx_to_tty()
1051 struct circ_buf *ring = &sport->rx_ring; in lpuart_copy_rx_to_tty()
1056 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); in lpuart_copy_rx_to_tty()
1060 lpuart32_read(&sport->port, UARTDATA); in lpuart_copy_rx_to_tty()
1063 sport->port.icount.parity++; in lpuart_copy_rx_to_tty()
1065 sport->port.icount.frame++; in lpuart_copy_rx_to_tty()
1068 unsigned char sr = readb(sport->port.membase + UARTSR1); in lpuart_copy_rx_to_tty()
1074 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1076 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1079 readb(sport->port.membase + UARTDR); in lpuart_copy_rx_to_tty()
1082 sport->port.icount.parity++; in lpuart_copy_rx_to_tty()
1084 sport->port.icount.frame++; in lpuart_copy_rx_to_tty()
1094 if (readb(sport->port.membase + UARTSFIFO) & in lpuart_copy_rx_to_tty()
1097 sport->port.membase + UARTSFIFO); in lpuart_copy_rx_to_tty()
1099 sport->port.membase + UARTCFIFO); in lpuart_copy_rx_to_tty()
1103 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1107 async_tx_ack(sport->dma_rx_desc); in lpuart_copy_rx_to_tty()
1109 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_copy_rx_to_tty()
1111 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); in lpuart_copy_rx_to_tty()
1113 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); in lpuart_copy_rx_to_tty()
1114 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_copy_rx_to_tty()
1119 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, in lpuart_copy_rx_to_tty()
1123 * ring->head points to the end of data already written by the DMA. in lpuart_copy_rx_to_tty()
1124 * ring->tail points to the beginning of data to be read by the in lpuart_copy_rx_to_tty()
1129 ring->head = sport->rx_sgl.length - state.residue; in lpuart_copy_rx_to_tty()
1130 BUG_ON(ring->head > sport->rx_sgl.length); in lpuart_copy_rx_to_tty()
1135 if (sport->port.sysrq) { in lpuart_copy_rx_to_tty()
1141 * At this point ring->head may point to the first byte right after the in lpuart_copy_rx_to_tty()
1143 * 0 <= ring->head <= sport->rx_sgl.length in lpuart_copy_rx_to_tty()
1145 * However ring->tail must always points inside the dma buffer: in lpuart_copy_rx_to_tty()
1146 * 0 <= ring->tail <= sport->rx_sgl.length - 1 in lpuart_copy_rx_to_tty()
1152 if (ring->head < ring->tail) { in lpuart_copy_rx_to_tty()
1153 count = sport->rx_sgl.length - ring->tail; in lpuart_copy_rx_to_tty()
1155 tty_insert_flip_string(port, ring->buf + ring->tail, count); in lpuart_copy_rx_to_tty()
1156 ring->tail = 0; in lpuart_copy_rx_to_tty()
1157 sport->port.icount.rx += count; in lpuart_copy_rx_to_tty()
1161 if (ring->tail < ring->head) { in lpuart_copy_rx_to_tty()
1162 count = ring->head - ring->tail; in lpuart_copy_rx_to_tty()
1163 tty_insert_flip_string(port, ring->buf + ring->tail, count); in lpuart_copy_rx_to_tty()
1164 /* Wrap ring->head if needed */ in lpuart_copy_rx_to_tty()
1165 if (ring->head >= sport->rx_sgl.length) in lpuart_copy_rx_to_tty()
1166 ring->head = 0; in lpuart_copy_rx_to_tty()
1167 ring->tail = ring->head; in lpuart_copy_rx_to_tty()
1168 sport->port.icount.rx += count; in lpuart_copy_rx_to_tty()
1172 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, in lpuart_copy_rx_to_tty()
1175 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_copy_rx_to_tty()
1178 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); in lpuart_copy_rx_to_tty()
1198 struct circ_buf *ring = &sport->rx_ring; in lpuart_start_rx_dma()
1200 int bits, baud; in lpuart_start_rx_dma() local
1201 struct tty_port *port = &sport->port.state->port; in lpuart_start_rx_dma()
1202 struct tty_struct *tty = port->tty; in lpuart_start_rx_dma()
1203 struct ktermios *termios = &tty->termios; in lpuart_start_rx_dma()
1204 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_start_rx_dma()
1206 baud = tty_get_baud_rate(tty); in lpuart_start_rx_dma()
1208 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; in lpuart_start_rx_dma()
1209 if (termios->c_cflag & PARENB) in lpuart_start_rx_dma()
1214 * 10ms at any baud rate. in lpuart_start_rx_dma()
1216 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; in lpuart_start_rx_dma()
1217 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); in lpuart_start_rx_dma()
1218 if (sport->rx_dma_rng_buf_len < 16) in lpuart_start_rx_dma()
1219 sport->rx_dma_rng_buf_len = 16; in lpuart_start_rx_dma()
1221 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); in lpuart_start_rx_dma()
1222 if (!ring->buf) in lpuart_start_rx_dma()
1223 return -ENOMEM; in lpuart_start_rx_dma()
1225 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); in lpuart_start_rx_dma()
1226 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, in lpuart_start_rx_dma()
1230 dev_err(sport->port.dev, "DMA Rx mapping error\n"); in lpuart_start_rx_dma()
1231 return -EINVAL; in lpuart_start_rx_dma()
1241 dev_err(sport->port.dev, in lpuart_start_rx_dma()
1246 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, in lpuart_start_rx_dma()
1247 sg_dma_address(&sport->rx_sgl), in lpuart_start_rx_dma()
1248 sport->rx_sgl.length, in lpuart_start_rx_dma()
1249 sport->rx_sgl.length / 2, in lpuart_start_rx_dma()
1252 if (!sport->dma_rx_desc) { in lpuart_start_rx_dma()
1253 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); in lpuart_start_rx_dma()
1254 return -EFAULT; in lpuart_start_rx_dma()
1257 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; in lpuart_start_rx_dma()
1258 sport->dma_rx_desc->callback_param = sport; in lpuart_start_rx_dma()
1259 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); in lpuart_start_rx_dma()
1263 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_start_rx_dma()
1265 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); in lpuart_start_rx_dma()
1267 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, in lpuart_start_rx_dma()
1268 sport->port.membase + UARTCR5); in lpuart_start_rx_dma()
1278 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_dma_rx_free()
1281 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); in lpuart_dma_rx_free()
1282 kfree(sport->rx_ring.buf); in lpuart_dma_rx_free()
1283 sport->rx_ring.tail = 0; in lpuart_dma_rx_free()
1284 sport->rx_ring.head = 0; in lpuart_dma_rx_free()
1285 sport->dma_rx_desc = NULL; in lpuart_dma_rx_free()
1286 sport->dma_rx_cookie = -EINVAL; in lpuart_dma_rx_free()
1295 u8 modem = readb(sport->port.membase + UARTMODEM) & in lpuart_config_rs485()
1297 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_config_rs485()
1300 rs485->delay_rts_before_send = 0; in lpuart_config_rs485()
1301 rs485->delay_rts_after_send = 0; in lpuart_config_rs485()
1302 rs485->flags &= ~SER_RS485_RX_DURING_TX; in lpuart_config_rs485()
1304 if (rs485->flags & SER_RS485_ENABLED) { in lpuart_config_rs485()
1305 /* Enable auto RS-485 RTS mode */ in lpuart_config_rs485()
1313 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | in lpuart_config_rs485()
1315 rs485->flags |= SER_RS485_RTS_ON_SEND; in lpuart_config_rs485()
1317 if (rs485->flags & SER_RS485_RTS_ON_SEND && in lpuart_config_rs485()
1318 rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart_config_rs485()
1319 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; in lpuart_config_rs485()
1327 if (rs485->flags & SER_RS485_RTS_ON_SEND) in lpuart_config_rs485()
1329 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart_config_rs485()
1334 sport->port.rs485 = *rs485; in lpuart_config_rs485()
1336 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_config_rs485()
1346 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) in lpuart32_config_rs485()
1348 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_config_rs485()
1351 rs485->delay_rts_before_send = 0; in lpuart32_config_rs485()
1352 rs485->delay_rts_after_send = 0; in lpuart32_config_rs485()
1353 rs485->flags &= ~SER_RS485_RX_DURING_TX; in lpuart32_config_rs485()
1355 if (rs485->flags & SER_RS485_ENABLED) { in lpuart32_config_rs485()
1356 /* Enable auto RS-485 RTS mode */ in lpuart32_config_rs485()
1364 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | in lpuart32_config_rs485()
1366 rs485->flags |= SER_RS485_RTS_ON_SEND; in lpuart32_config_rs485()
1368 if (rs485->flags & SER_RS485_RTS_ON_SEND && in lpuart32_config_rs485()
1369 rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart32_config_rs485()
1370 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; in lpuart32_config_rs485()
1378 if (rs485->flags & SER_RS485_RTS_ON_SEND) in lpuart32_config_rs485()
1380 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart32_config_rs485()
1385 sport->port.rs485 = *rs485; in lpuart32_config_rs485()
1387 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_config_rs485()
1396 reg = readb(port->membase + UARTMODEM); in lpuart_get_mctrl()
1418 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) { in lpuart_set_mctrl()
1419 temp = readb(sport->port.membase + UARTMODEM) & in lpuart_set_mctrl()
1428 writeb(temp, port->membase + UARTMODEM); in lpuart_set_mctrl()
1441 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; in lpuart_break_ctl()
1446 writeb(temp, port->membase + UARTCR2); in lpuart_break_ctl()
1466 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1470 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1472 val = readb(sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1474 sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1478 sport->port.membase + UARTCFIFO); in lpuart_setup_watermark()
1481 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_setup_watermark()
1482 readb(sport->port.membase + UARTDR); in lpuart_setup_watermark()
1483 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); in lpuart_setup_watermark()
1486 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_setup_watermark()
1487 writeb(1, sport->port.membase + UARTRWFIFO); in lpuart_setup_watermark()
1490 writeb(cr2_saved, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1499 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1501 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1509 ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_setup_watermark()
1513 lpuart32_write(&sport->port, ctrl, UARTCTRL); in lpuart32_setup_watermark()
1516 val = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_setup_watermark()
1519 lpuart32_write(&sport->port, val, UARTFIFO); in lpuart32_setup_watermark()
1523 lpuart32_write(&sport->port, val, UARTWATER); in lpuart32_setup_watermark()
1526 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); in lpuart32_setup_watermark()
1535 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_setup_watermark_enable()
1537 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_setup_watermark_enable()
1542 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); in rx_dma_timer_init()
1543 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; in rx_dma_timer_init()
1544 add_timer(&sport->lpuart_timer); in rx_dma_timer_init()
1549 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); in lpuart_request_dma()
1550 if (IS_ERR(sport->dma_tx_chan)) { in lpuart_request_dma()
1551 dev_dbg_once(sport->port.dev, in lpuart_request_dma()
1553 PTR_ERR(sport->dma_tx_chan)); in lpuart_request_dma()
1554 sport->dma_tx_chan = NULL; in lpuart_request_dma()
1557 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); in lpuart_request_dma()
1558 if (IS_ERR(sport->dma_rx_chan)) { in lpuart_request_dma()
1559 dev_dbg_once(sport->port.dev, in lpuart_request_dma()
1561 PTR_ERR(sport->dma_rx_chan)); in lpuart_request_dma()
1562 sport->dma_rx_chan = NULL; in lpuart_request_dma()
1571 if (uart_console(&sport->port)) in lpuart_tx_dma_startup()
1574 if (!sport->dma_tx_chan) in lpuart_tx_dma_startup()
1577 ret = lpuart_dma_tx_request(&sport->port); in lpuart_tx_dma_startup()
1581 init_waitqueue_head(&sport->dma_wait); in lpuart_tx_dma_startup()
1582 sport->lpuart_dma_tx_use = true; in lpuart_tx_dma_startup()
1584 uartbaud = lpuart32_read(&sport->port, UARTBAUD); in lpuart_tx_dma_startup()
1585 lpuart32_write(&sport->port, in lpuart_tx_dma_startup()
1588 writeb(readb(sport->port.membase + UARTCR5) | in lpuart_tx_dma_startup()
1589 UARTCR5_TDMAS, sport->port.membase + UARTCR5); in lpuart_tx_dma_startup()
1595 sport->lpuart_dma_tx_use = false; in lpuart_tx_dma_startup()
1603 if (uart_console(&sport->port)) in lpuart_rx_dma_startup()
1606 if (!sport->dma_rx_chan) in lpuart_rx_dma_startup()
1614 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); in lpuart_rx_dma_startup()
1615 if (!sport->dma_rx_timeout) in lpuart_rx_dma_startup()
1616 sport->dma_rx_timeout = 1; in lpuart_rx_dma_startup()
1618 sport->lpuart_dma_rx_use = true; in lpuart_rx_dma_startup()
1621 if (sport->port.has_sysrq && !lpuart_is_32(sport)) { in lpuart_rx_dma_startup()
1622 cr3 = readb(sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1624 writeb(cr3, sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1630 sport->lpuart_dma_rx_use = false; in lpuart_rx_dma_startup()
1640 temp = readb(sport->port.membase + UARTPFIFO); in lpuart_startup()
1642 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & in lpuart_startup()
1644 sport->port.fifosize = sport->txfifo_size; in lpuart_startup()
1646 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & in lpuart_startup()
1651 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_startup()
1658 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_startup()
1667 if (sport->lpuart_dma_rx_use) { in lpuart32_configure()
1669 temp = lpuart32_read(&sport->port, UARTWATER); in lpuart32_configure()
1671 lpuart32_write(&sport->port, temp, UARTWATER); in lpuart32_configure()
1673 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_configure()
1674 if (!sport->lpuart_dma_rx_use) in lpuart32_configure()
1676 if (!sport->lpuart_dma_tx_use) in lpuart32_configure()
1678 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_configure()
1688 temp = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_startup()
1690 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & in lpuart32_startup()
1692 sport->port.fifosize = sport->txfifo_size; in lpuart32_startup()
1694 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & in lpuart32_startup()
1703 sport->rxfifo_size = 16; in lpuart32_startup()
1704 sport->txfifo_size = 16; in lpuart32_startup()
1705 sport->port.fifosize = sport->txfifo_size; in lpuart32_startup()
1710 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_startup()
1719 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_startup()
1725 if (sport->lpuart_dma_rx_use) { in lpuart_dma_shutdown()
1726 del_timer_sync(&sport->lpuart_timer); in lpuart_dma_shutdown()
1727 lpuart_dma_rx_free(&sport->port); in lpuart_dma_shutdown()
1728 sport->lpuart_dma_rx_use = false; in lpuart_dma_shutdown()
1731 if (sport->lpuart_dma_tx_use) { in lpuart_dma_shutdown()
1732 if (wait_event_interruptible(sport->dma_wait, in lpuart_dma_shutdown()
1733 !sport->dma_tx_in_progress) != false) { in lpuart_dma_shutdown()
1734 sport->dma_tx_in_progress = false; in lpuart_dma_shutdown()
1735 dmaengine_terminate_all(sport->dma_tx_chan); in lpuart_dma_shutdown()
1737 sport->lpuart_dma_tx_use = false; in lpuart_dma_shutdown()
1740 if (sport->dma_tx_chan) in lpuart_dma_shutdown()
1741 dma_release_channel(sport->dma_tx_chan); in lpuart_dma_shutdown()
1742 if (sport->dma_rx_chan) in lpuart_dma_shutdown()
1743 dma_release_channel(sport->dma_rx_chan); in lpuart_dma_shutdown()
1752 spin_lock_irqsave(&port->lock, flags); in lpuart_shutdown()
1755 temp = readb(port->membase + UARTCR2); in lpuart_shutdown()
1758 writeb(temp, port->membase + UARTCR2); in lpuart_shutdown()
1760 spin_unlock_irqrestore(&port->lock, flags); in lpuart_shutdown()
1772 spin_lock_irqsave(&port->lock, flags); in lpuart32_shutdown()
1780 spin_unlock_irqrestore(&port->lock, flags); in lpuart32_shutdown()
1792 unsigned int baud; in lpuart_set_termios() local
1793 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in lpuart_set_termios()
1796 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); in lpuart_set_termios()
1797 old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_set_termios()
1798 cr3 = readb(sport->port.membase + UARTCR3); in lpuart_set_termios()
1799 cr4 = readb(sport->port.membase + UARTCR4); in lpuart_set_termios()
1800 bdh = readb(sport->port.membase + UARTBDH); in lpuart_set_termios()
1801 modem = readb(sport->port.membase + UARTMODEM); in lpuart_set_termios()
1805 * - (7,e/o,1) in lpuart_set_termios()
1806 * - (8,n,1) in lpuart_set_termios()
1807 * - (8,m/s,1) in lpuart_set_termios()
1808 * - (8,e/o,1) in lpuart_set_termios()
1810 while ((termios->c_cflag & CSIZE) != CS8 && in lpuart_set_termios()
1811 (termios->c_cflag & CSIZE) != CS7) { in lpuart_set_termios()
1812 termios->c_cflag &= ~CSIZE; in lpuart_set_termios()
1813 termios->c_cflag |= old_csize; in lpuart_set_termios()
1817 if ((termios->c_cflag & CSIZE) == CS8 || in lpuart_set_termios()
1818 (termios->c_cflag & CSIZE) == CS7) in lpuart_set_termios()
1821 if (termios->c_cflag & CMSPAR) { in lpuart_set_termios()
1822 if ((termios->c_cflag & CSIZE) != CS8) { in lpuart_set_termios()
1823 termios->c_cflag &= ~CSIZE; in lpuart_set_termios()
1824 termios->c_cflag |= CS8; in lpuart_set_termios()
1830 * When auto RS-485 RTS mode is enabled, in lpuart_set_termios()
1833 if (sport->port.rs485.flags & SER_RS485_ENABLED) in lpuart_set_termios()
1834 termios->c_cflag &= ~CRTSCTS; in lpuart_set_termios()
1836 if (termios->c_cflag & CRTSCTS) in lpuart_set_termios()
1841 termios->c_cflag &= ~CSTOPB; in lpuart_set_termios()
1843 /* parity must be enabled when CS7 to match 8-bits format */ in lpuart_set_termios()
1844 if ((termios->c_cflag & CSIZE) == CS7) in lpuart_set_termios()
1845 termios->c_cflag |= PARENB; in lpuart_set_termios()
1847 if (termios->c_cflag & PARENB) { in lpuart_set_termios()
1848 if (termios->c_cflag & CMSPAR) { in lpuart_set_termios()
1850 if (termios->c_cflag & PARODD) in lpuart_set_termios()
1856 if ((termios->c_cflag & CSIZE) == CS8) in lpuart_set_termios()
1858 if (termios->c_cflag & PARODD) in lpuart_set_termios()
1868 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); in lpuart_set_termios()
1872 * baud rate and restart Rx DMA path. in lpuart_set_termios()
1874 * Since timer function acqures sport->port.lock, need to stop before in lpuart_set_termios()
1877 if (old && sport->lpuart_dma_rx_use) { in lpuart_set_termios()
1878 del_timer_sync(&sport->lpuart_timer); in lpuart_set_termios()
1879 lpuart_dma_rx_free(&sport->port); in lpuart_set_termios()
1882 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_set_termios()
1884 sport->port.read_status_mask = 0; in lpuart_set_termios()
1885 if (termios->c_iflag & INPCK) in lpuart_set_termios()
1886 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; in lpuart_set_termios()
1887 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in lpuart_set_termios()
1888 sport->port.read_status_mask |= UARTSR1_FE; in lpuart_set_termios()
1891 sport->port.ignore_status_mask = 0; in lpuart_set_termios()
1892 if (termios->c_iflag & IGNPAR) in lpuart_set_termios()
1893 sport->port.ignore_status_mask |= UARTSR1_PE; in lpuart_set_termios()
1894 if (termios->c_iflag & IGNBRK) { in lpuart_set_termios()
1895 sport->port.ignore_status_mask |= UARTSR1_FE; in lpuart_set_termios()
1900 if (termios->c_iflag & IGNPAR) in lpuart_set_termios()
1901 sport->port.ignore_status_mask |= UARTSR1_OR; in lpuart_set_termios()
1904 /* update the per-port timeout */ in lpuart_set_termios()
1905 uart_update_timeout(port, termios->c_cflag, baud); in lpuart_set_termios()
1908 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); in lpuart_set_termios()
1912 sport->port.membase + UARTCR2); in lpuart_set_termios()
1914 sbr = sport->port.uartclk / (16 * baud); in lpuart_set_termios()
1915 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; in lpuart_set_termios()
1920 writeb(cr4 | brfa, sport->port.membase + UARTCR4); in lpuart_set_termios()
1921 writeb(bdh, sport->port.membase + UARTBDH); in lpuart_set_termios()
1922 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); in lpuart_set_termios()
1923 writeb(cr3, sport->port.membase + UARTCR3); in lpuart_set_termios()
1924 writeb(cr1, sport->port.membase + UARTCR1); in lpuart_set_termios()
1925 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_set_termios()
1928 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_set_termios()
1930 if (old && sport->lpuart_dma_rx_use) { in lpuart_set_termios()
1934 sport->lpuart_dma_rx_use = false; in lpuart_set_termios()
1937 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_set_termios()
1945 u32 clk = port->uartclk; in __lpuart32_serial_setbrg()
1948 * The idea is to use the best OSR (over-sampling rate) possible. in __lpuart32_serial_setbrg()
1949 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. in __lpuart32_serial_setbrg()
1954 * Baud Rate = baud clock / ((OSR+1) × SBR) in __lpuart32_serial_setbrg()
1967 * calculate the baud rate difference based on the temporary in __lpuart32_serial_setbrg()
1970 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; in __lpuart32_serial_setbrg()
1974 if (tmp_diff > (baudrate - tmp)) { in __lpuart32_serial_setbrg()
1975 tmp_diff = baudrate - tmp; in __lpuart32_serial_setbrg()
1994 dev_warn(port->dev, in __lpuart32_serial_setbrg()
1995 "unacceptable baud rate difference of more than 3%%\n"); in __lpuart32_serial_setbrg()
2003 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; in __lpuart32_serial_setbrg()
2019 __lpuart32_serial_setbrg(&sport->port, baudrate, in lpuart32_serial_setbrg()
2020 sport->lpuart_dma_rx_use, in lpuart32_serial_setbrg()
2021 sport->lpuart_dma_tx_use); in lpuart32_serial_setbrg()
2032 unsigned int baud; in lpuart32_set_termios() local
2033 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in lpuart32_set_termios()
2035 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_set_termios()
2036 modem = lpuart32_read(&sport->port, UARTMODIR); in lpuart32_set_termios()
2040 * - (7,e/o,1) in lpuart32_set_termios()
2041 * - (8,n,1) in lpuart32_set_termios()
2042 * - (8,m/s,1) in lpuart32_set_termios()
2043 * - (8,e/o,1) in lpuart32_set_termios()
2045 while ((termios->c_cflag & CSIZE) != CS8 && in lpuart32_set_termios()
2046 (termios->c_cflag & CSIZE) != CS7) { in lpuart32_set_termios()
2047 termios->c_cflag &= ~CSIZE; in lpuart32_set_termios()
2048 termios->c_cflag |= old_csize; in lpuart32_set_termios()
2052 if ((termios->c_cflag & CSIZE) == CS8 || in lpuart32_set_termios()
2053 (termios->c_cflag & CSIZE) == CS7) in lpuart32_set_termios()
2056 if (termios->c_cflag & CMSPAR) { in lpuart32_set_termios()
2057 if ((termios->c_cflag & CSIZE) != CS8) { in lpuart32_set_termios()
2058 termios->c_cflag &= ~CSIZE; in lpuart32_set_termios()
2059 termios->c_cflag |= CS8; in lpuart32_set_termios()
2065 * When auto RS-485 RTS mode is enabled, in lpuart32_set_termios()
2068 if (sport->port.rs485.flags & SER_RS485_ENABLED) in lpuart32_set_termios()
2069 termios->c_cflag &= ~CRTSCTS; in lpuart32_set_termios()
2071 if (termios->c_cflag & CRTSCTS) { in lpuart32_set_termios()
2074 termios->c_cflag &= ~CRTSCTS; in lpuart32_set_termios()
2078 if (termios->c_cflag & CSTOPB) in lpuart32_set_termios()
2079 termios->c_cflag &= ~CSTOPB; in lpuart32_set_termios()
2081 /* parity must be enabled when CS7 to match 8-bits format */ in lpuart32_set_termios()
2082 if ((termios->c_cflag & CSIZE) == CS7) in lpuart32_set_termios()
2083 termios->c_cflag |= PARENB; in lpuart32_set_termios()
2085 if ((termios->c_cflag & PARENB)) { in lpuart32_set_termios()
2086 if (termios->c_cflag & CMSPAR) { in lpuart32_set_termios()
2091 if ((termios->c_cflag & CSIZE) == CS8) in lpuart32_set_termios()
2093 if (termios->c_cflag & PARODD) in lpuart32_set_termios()
2103 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); in lpuart32_set_termios()
2107 * baud rate and restart Rx DMA path. in lpuart32_set_termios()
2109 * Since timer function acqures sport->port.lock, need to stop before in lpuart32_set_termios()
2112 if (old && sport->lpuart_dma_rx_use) { in lpuart32_set_termios()
2113 del_timer_sync(&sport->lpuart_timer); in lpuart32_set_termios()
2114 lpuart_dma_rx_free(&sport->port); in lpuart32_set_termios()
2117 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_set_termios()
2119 sport->port.read_status_mask = 0; in lpuart32_set_termios()
2120 if (termios->c_iflag & INPCK) in lpuart32_set_termios()
2121 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; in lpuart32_set_termios()
2122 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in lpuart32_set_termios()
2123 sport->port.read_status_mask |= UARTSTAT_FE; in lpuart32_set_termios()
2126 sport->port.ignore_status_mask = 0; in lpuart32_set_termios()
2127 if (termios->c_iflag & IGNPAR) in lpuart32_set_termios()
2128 sport->port.ignore_status_mask |= UARTSTAT_PE; in lpuart32_set_termios()
2129 if (termios->c_iflag & IGNBRK) { in lpuart32_set_termios()
2130 sport->port.ignore_status_mask |= UARTSTAT_FE; in lpuart32_set_termios()
2135 if (termios->c_iflag & IGNPAR) in lpuart32_set_termios()
2136 sport->port.ignore_status_mask |= UARTSTAT_OR; in lpuart32_set_termios()
2139 /* update the per-port timeout */ in lpuart32_set_termios()
2140 uart_update_timeout(port, termios->c_cflag, baud); in lpuart32_set_termios()
2143 lpuart32_write(&sport->port, 0, UARTMODIR); in lpuart32_set_termios()
2144 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); in lpuart32_set_termios()
2147 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), in lpuart32_set_termios()
2150 lpuart32_serial_setbrg(sport, baud); in lpuart32_set_termios()
2151 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_set_termios()
2152 lpuart32_write(&sport->port, ctrl, UARTCTRL); in lpuart32_set_termios()
2155 if (old && sport->lpuart_dma_rx_use) { in lpuart32_set_termios()
2159 sport->lpuart_dma_rx_use = false; in lpuart32_set_termios()
2162 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_set_termios()
2184 port->type = PORT_LPUART; in lpuart_config_port()
2191 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) in lpuart_verify_port()
2192 ret = -EINVAL; in lpuart_verify_port()
2193 if (port->irq != ser->irq) in lpuart_verify_port()
2194 ret = -EINVAL; in lpuart_verify_port()
2195 if (ser->io_type != UPIO_MEM) in lpuart_verify_port()
2196 ret = -EINVAL; in lpuart_verify_port()
2197 if (port->uartclk / 16 != ser->baud_base) in lpuart_verify_port()
2198 ret = -EINVAL; in lpuart_verify_port()
2199 if (port->iobase != ser->port) in lpuart_verify_port()
2200 ret = -EINVAL; in lpuart_verify_port()
2201 if (ser->hub6 != 0) in lpuart_verify_port()
2202 ret = -EINVAL; in lpuart_verify_port()
2260 writeb(ch, port->membase + UARTDR); in lpuart_console_putchar()
2272 struct lpuart_port *sport = lpuart_ports[co->index]; in lpuart_console_write()
2277 if (sport->port.sysrq || oops_in_progress) in lpuart_console_write()
2278 locked = spin_trylock_irqsave(&sport->port.lock, flags); in lpuart_console_write()
2280 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_console_write()
2283 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_console_write()
2286 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2288 uart_console_write(&sport->port, s, count, lpuart_console_putchar); in lpuart_console_write()
2291 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); in lpuart_console_write()
2293 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2296 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_console_write()
2302 struct lpuart_port *sport = lpuart_ports[co->index]; in lpuart32_console_write()
2307 if (sport->port.sysrq || oops_in_progress) in lpuart32_console_write()
2308 locked = spin_trylock_irqsave(&sport->port.lock, flags); in lpuart32_console_write()
2310 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_console_write()
2313 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_write()
2316 lpuart32_write(&sport->port, cr, UARTCTRL); in lpuart32_console_write()
2318 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); in lpuart32_console_write()
2321 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); in lpuart32_console_write()
2323 lpuart32_write(&sport->port, old_cr, UARTCTRL); in lpuart32_console_write()
2326 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_console_write()
2334 lpuart_console_get_options(struct lpuart_port *sport, int *baud, in lpuart_console_get_options() argument
2340 cr = readb(sport->port.membase + UARTCR2); in lpuart_console_get_options()
2347 cr = readb(sport->port.membase + UARTCR1); in lpuart_console_get_options()
2362 bdh = readb(sport->port.membase + UARTBDH); in lpuart_console_get_options()
2364 bdl = readb(sport->port.membase + UARTBDL); in lpuart_console_get_options()
2368 brfa = readb(sport->port.membase + UARTCR4); in lpuart_console_get_options()
2373 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) in lpuart_console_get_options()
2377 if (*baud != baud_raw) in lpuart_console_get_options()
2378 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" in lpuart_console_get_options()
2379 "from %d to %d\n", baud_raw, *baud); in lpuart_console_get_options()
2383 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, in lpuart32_console_get_options() argument
2389 cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_get_options()
2396 cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_get_options()
2411 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart32_console_get_options()
2419 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) in lpuart32_console_get_options()
2423 if (*baud != baud_raw) in lpuart32_console_get_options()
2424 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" in lpuart32_console_get_options()
2425 "from %d to %d\n", baud_raw, *baud); in lpuart32_console_get_options()
2431 int baud = 115200; in lpuart_console_setup() local
2441 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) in lpuart_console_setup()
2442 co->index = 0; in lpuart_console_setup()
2444 sport = lpuart_ports[co->index]; in lpuart_console_setup()
2446 return -ENODEV; in lpuart_console_setup()
2449 uart_parse_options(options, &baud, &parity, &bits, &flow); in lpuart_console_setup()
2452 lpuart32_console_get_options(sport, &baud, &parity, &bits); in lpuart_console_setup()
2454 lpuart_console_get_options(sport, &baud, &parity, &bits); in lpuart_console_setup()
2461 return uart_set_options(&sport->port, co, baud, parity, bits, flow); in lpuart_console_setup()
2471 .index = -1,
2481 .index = -1,
2487 struct earlycon_device *dev = con->data; in lpuart_early_write()
2489 uart_console_write(&dev->port, s, n, lpuart_console_putchar); in lpuart_early_write()
2494 struct earlycon_device *dev = con->data; in lpuart32_early_write()
2496 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); in lpuart32_early_write()
2502 if (!device->port.membase) in lpuart_early_console_setup()
2503 return -ENODEV; in lpuart_early_console_setup()
2505 device->con->write = lpuart_early_write; in lpuart_early_console_setup()
2512 if (!device->port.membase) in lpuart32_early_console_setup()
2513 return -ENODEV; in lpuart32_early_console_setup()
2515 if (device->port.iotype != UPIO_MEM32) in lpuart32_early_console_setup()
2516 device->port.iotype = UPIO_MEM32BE; in lpuart32_early_console_setup()
2518 device->con->write = lpuart32_early_write; in lpuart32_early_console_setup()
2527 if (!device->port.membase) in ls1028a_early_console_setup()
2528 return -ENODEV; in ls1028a_early_console_setup()
2530 device->port.iotype = UPIO_MEM32; in ls1028a_early_console_setup()
2531 device->con->write = lpuart32_early_write; in ls1028a_early_console_setup()
2534 if (device->port.uartclk && device->baud) in ls1028a_early_console_setup()
2535 __lpuart32_serial_setbrg(&device->port, device->baud, in ls1028a_early_console_setup()
2539 cr = lpuart32_read(&device->port, UARTCTRL); in ls1028a_early_console_setup()
2541 lpuart32_write(&device->port, cr, UARTCTRL); in ls1028a_early_console_setup()
2549 if (!device->port.membase) in lpuart32_imx_early_console_setup()
2550 return -ENODEV; in lpuart32_imx_early_console_setup()
2552 device->port.iotype = UPIO_MEM32; in lpuart32_imx_early_console_setup()
2553 device->port.membase += IMX_REG_OFF; in lpuart32_imx_early_console_setup()
2554 device->con->write = lpuart32_early_write; in lpuart32_imx_early_console_setup()
2558 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2559 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2560 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2561 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2562 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
2584 &pdev->dev); in lpuart_probe()
2585 const struct lpuart_soc_data *sdata = of_id->data; in lpuart_probe()
2586 struct device_node *np = pdev->dev.of_node; in lpuart_probe()
2591 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in lpuart_probe()
2593 return -ENOMEM; in lpuart_probe()
2596 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); in lpuart_probe()
2597 if (IS_ERR(sport->port.membase)) in lpuart_probe()
2598 return PTR_ERR(sport->port.membase); in lpuart_probe()
2600 sport->port.membase += sdata->reg_off; in lpuart_probe()
2601 sport->port.mapbase = res->start + sdata->reg_off; in lpuart_probe()
2602 sport->port.dev = &pdev->dev; in lpuart_probe()
2603 sport->port.type = PORT_LPUART; in lpuart_probe()
2604 sport->devtype = sdata->devtype; in lpuart_probe()
2608 sport->port.irq = ret; in lpuart_probe()
2609 sport->port.iotype = sdata->iotype; in lpuart_probe()
2611 sport->port.ops = &lpuart32_pops; in lpuart_probe()
2613 sport->port.ops = &lpuart_pops; in lpuart_probe()
2614 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); in lpuart_probe()
2615 sport->port.flags = UPF_BOOT_AUTOCONF; in lpuart_probe()
2618 sport->port.rs485_config = lpuart32_config_rs485; in lpuart_probe()
2620 sport->port.rs485_config = lpuart_config_rs485; in lpuart_probe()
2622 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); in lpuart_probe()
2623 if (IS_ERR(sport->ipg_clk)) { in lpuart_probe()
2624 ret = PTR_ERR(sport->ipg_clk); in lpuart_probe()
2625 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret); in lpuart_probe()
2629 sport->baud_clk = NULL; in lpuart_probe()
2631 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); in lpuart_probe()
2632 if (IS_ERR(sport->baud_clk)) { in lpuart_probe()
2633 ret = PTR_ERR(sport->baud_clk); in lpuart_probe()
2634 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret); in lpuart_probe()
2641 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); in lpuart_probe()
2645 dev_err(&pdev->dev, "serial%d out of range\n", ret); in lpuart_probe()
2646 return -EINVAL; in lpuart_probe()
2648 sport->port.line = ret; in lpuart_probe()
2653 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); in lpuart_probe()
2655 lpuart_ports[sport->port.line] = sport; in lpuart_probe()
2657 platform_set_drvdata(pdev, &sport->port); in lpuart_probe()
2661 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0, in lpuart_probe()
2665 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0, in lpuart_probe()
2672 ret = uart_get_rs485_mode(&sport->port); in lpuart_probe()
2676 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX) in lpuart_probe()
2677 dev_err(&pdev->dev, "driver doesn't support RX during TX\n"); in lpuart_probe()
2679 if (sport->port.rs485.delay_rts_before_send || in lpuart_probe()
2680 sport->port.rs485.delay_rts_after_send) in lpuart_probe()
2681 dev_err(&pdev->dev, "driver doesn't support RTS delays\n"); in lpuart_probe()
2683 ret = uart_add_one_port(&lpuart_reg, &sport->port); in lpuart_probe()
2700 uart_remove_one_port(&lpuart_reg, &sport->port); in lpuart_remove()
2704 if (sport->dma_tx_chan) in lpuart_remove()
2705 dma_release_channel(sport->dma_tx_chan); in lpuart_remove()
2707 if (sport->dma_rx_chan) in lpuart_remove()
2708 dma_release_channel(sport->dma_rx_chan); in lpuart_remove()
2721 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart_suspend()
2723 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart_suspend()
2726 temp = readb(sport->port.membase + UARTCR2); in lpuart_suspend()
2728 writeb(temp, sport->port.membase + UARTCR2); in lpuart_suspend()
2731 uart_suspend_port(&lpuart_reg, &sport->port); in lpuart_suspend()
2734 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); in lpuart_suspend()
2736 if (sport->lpuart_dma_rx_use) { in lpuart_suspend()
2739 * non-idle DMA channels. If port wakeup is enabled or if port in lpuart_suspend()
2745 del_timer_sync(&sport->lpuart_timer); in lpuart_suspend()
2746 lpuart_dma_rx_free(&sport->port); in lpuart_suspend()
2751 temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_suspend()
2752 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, in lpuart_suspend()
2755 writeb(readb(sport->port.membase + UARTCR5) & in lpuart_suspend()
2756 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); in lpuart_suspend()
2760 if (sport->lpuart_dma_tx_use) { in lpuart_suspend()
2761 sport->dma_tx_in_progress = false; in lpuart_suspend()
2762 dmaengine_terminate_all(sport->dma_tx_chan); in lpuart_suspend()
2765 if (sport->port.suspended && !irq_wake) in lpuart_suspend()
2774 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); in lpuart_resume()
2776 if (sport->port.suspended && !irq_wake) in lpuart_resume()
2784 if (sport->lpuart_dma_rx_use) { in lpuart_resume()
2789 sport->lpuart_dma_rx_use = false; in lpuart_resume()
2798 uart_resume_port(&lpuart_reg, &sport->port); in lpuart_resume()
2809 .name = "fsl-lpuart",