Lines Matching refs:ubrlcr
210 unsigned int ubrlcr; in uart_clps711x_break_ctl() local
212 ubrlcr = readl(port->membase + UBRLCR_OFFSET); in uart_clps711x_break_ctl()
214 ubrlcr |= UBRLCR_BREAK; in uart_clps711x_break_ctl()
216 ubrlcr &= ~UBRLCR_BREAK; in uart_clps711x_break_ctl()
217 writel(ubrlcr, port->membase + UBRLCR_OFFSET); in uart_clps711x_break_ctl()
256 u32 ubrlcr; in uart_clps711x_set_termios() local
270 ubrlcr = UBRLCR_WRDLEN5; in uart_clps711x_set_termios()
273 ubrlcr = UBRLCR_WRDLEN6; in uart_clps711x_set_termios()
276 ubrlcr = UBRLCR_WRDLEN7; in uart_clps711x_set_termios()
280 ubrlcr = UBRLCR_WRDLEN8; in uart_clps711x_set_termios()
285 ubrlcr |= UBRLCR_XSTOP; in uart_clps711x_set_termios()
288 ubrlcr |= UBRLCR_PRTEN; in uart_clps711x_set_termios()
290 ubrlcr |= UBRLCR_EVENPRT; in uart_clps711x_set_termios()
294 ubrlcr |= UBRLCR_FIFOEN; in uart_clps711x_set_termios()
309 writel(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET); in uart_clps711x_set_termios()
386 u32 ubrlcr; in uart_clps711x_console_setup() local
402 ubrlcr = readl(port->membase + UBRLCR_OFFSET); in uart_clps711x_console_setup()
404 if (ubrlcr & UBRLCR_PRTEN) { in uart_clps711x_console_setup()
405 if (ubrlcr & UBRLCR_EVENPRT) in uart_clps711x_console_setup()
411 if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7) in uart_clps711x_console_setup()
414 quot = ubrlcr & UBRLCR_BAUD_MASK; in uart_clps711x_console_setup()