Lines Matching +full:0 +full:x10070000

29 #define EXYNOS_TMU_REG_TRIMINFO		0x0
30 #define EXYNOS_TMU_REG_CONTROL 0x20
31 #define EXYNOS_TMU_REG_STATUS 0x28
32 #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
33 #define EXYNOS_TMU_REG_INTEN 0x70
34 #define EXYNOS_TMU_REG_INTSTAT 0x74
35 #define EXYNOS_TMU_REG_INTCLEAR 0x78
37 #define EXYNOS_TMU_TEMP_MASK 0xff
39 #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f
40 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf
42 #define EXYNOS_TMU_CORE_EN_SHIFT 0
45 #define EXYNOS_TMU_TRIMINFO_CON1 0x10
48 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
49 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
52 #define EXYNOS_TMU_TRIMINFO_CON2 0x14
53 #define EXYNOS_THD_TEMP_RISE 0x50
54 #define EXYNOS_THD_TEMP_FALL 0x54
55 #define EXYNOS_EMUL_CON 0x80
58 #define EXYNOS_TRIMINFO_25_SHIFT 0
61 #define EXYNOS_TMU_TRIP_MODE_MASK 0x7
64 #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0
67 #define EXYNOS_EMUL_TIME 0x57F0
68 #define EXYNOS_EMUL_TIME_MASK 0xffff
71 #define EXYNOS_EMUL_DATA_MASK 0xFF
72 #define EXYNOS_EMUL_ENABLE 0x1
75 #define EXYNOS5260_TMU_REG_INTEN 0xC0
76 #define EXYNOS5260_TMU_REG_INTSTAT 0xC4
77 #define EXYNOS5260_TMU_REG_INTCLEAR 0xC8
78 #define EXYNOS5260_EMUL_CON 0x100
85 #define EXYNOS5433_THD_TEMP_RISE3_0 0x050
86 #define EXYNOS5433_THD_TEMP_RISE7_4 0x054
87 #define EXYNOS5433_THD_TEMP_FALL3_0 0x060
88 #define EXYNOS5433_THD_TEMP_FALL7_4 0x064
89 #define EXYNOS5433_TMU_REG_INTEN 0x0c0
90 #define EXYNOS5433_TMU_REG_INTPEND 0x0c8
91 #define EXYNOS5433_TMU_EMUL_CON 0x110
92 #define EXYNOS5433_TMU_PD_DET_EN 0x130
97 (0xf << EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT)
100 #define EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING 0
105 #define EXYNOS5433_G3D_BASE 0x10070000
108 #define EXYNOS7_THD_TEMP_RISE7_6 0x50
109 #define EXYNOS7_THD_TEMP_FALL7_6 0x60
110 #define EXYNOS7_TMU_REG_INTEN 0x110
111 #define EXYNOS7_TMU_REG_INTPEND 0x118
112 #define EXYNOS7_TMU_REG_EMUL_CON 0x160
114 #define EXYNOS7_TMU_TEMP_MASK 0x1ff
116 #define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0
118 #define EXYNOS7_EMUL_DATA_MASK 0x1ff
159 * 0 < gain <= 15
162 * 0 < reference_voltage <= 31
266 int ret = 0, temp, hyst; in exynos_tmu_initialize()
305 for (i = 0; i < ntrips; i++) { in exynos_tmu_initialize()
369 ref = trips[0].temperature / MCELSIUS; in exynos4210_tmu_set_trip_temp()
371 if (trip == 0) { in exynos4210_tmu_set_trip_temp()
399 th &= ~(0xff << 8 * trip); in exynos4412_tmu_set_trip_temp()
416 th &= ~(0xff << 8 * trip); in exynos4412_tmu_set_trip_hyst()
464 th &= ~(0xff << j * 8); in exynos5433_tmu_set_trip_temp()
484 th &= ~(0xff << j * 8); in exynos5433_tmu_set_trip_hyst()
501 dev_info(&pdev->dev, "Temperature sensor ID: 0x%x\n", sensor_id); in exynos5433_tmu_initialize()
565 unsigned int con, interrupt_en = 0, i; in exynos4210_tmu_control()
570 for (i = 0; i < data->ntrip; i++) { in exynos4210_tmu_control()
595 unsigned int con, interrupt_en = 0, pd_det_en, i; in exynos5433_tmu_control()
600 for (i = 0; i < data->ntrip; i++) { in exynos5433_tmu_control()
615 pd_det_en = on ? EXYNOS5433_PD_DET_EN : 0; in exynos5433_tmu_control()
626 unsigned int con, interrupt_en = 0, i; in exynos7_tmu_control()
631 for (i = 0; i < data->ntrip; i++) { in exynos7_tmu_control()
656 int value, ret = 0; in exynos_get_temp()
671 if (value < 0) in exynos_get_temp()
747 return 0; in exynos_tmu_set_emulation()
877 if (data->id < 0) in exynos_map_dt_data()
878 data->id = 0; in exynos_map_dt_data()
880 data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); in exynos_map_dt_data()
881 if (data->irq <= 0) { in exynos_map_dt_data()
886 if (of_address_to_resource(pdev->dev.of_node, 0, &res)) { in exynos_map_dt_data()
887 dev_err(&pdev->dev, "failed to get Resource 0\n"); in exynos_map_dt_data()
935 data->min_efuse_value = 0; in exynos_map_dt_data()
983 return 0; in exynos_map_dt_data()
997 return 0; in exynos_map_dt_data()
1094 data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data, in exynos_tmu_probe()
1118 return 0; in exynos_tmu_probe()
1152 return 0; in exynos_tmu_remove()
1160 return 0; in exynos_tmu_suspend()
1170 return 0; in exynos_tmu_resume()