30 	TSHUT_MODE_CRU = 0,
37  * 0: low active, 1: high active
40 	TSHUT_LOW_ACTIVE = 0,
49 	SENSOR_CPU = 0,
59 	ADC_DECREMENT = 0,
96  * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
97  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
174  * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
175  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
210 #define TSADCV2_USER_CON			0x00
211 #define TSADCV2_AUTO_CON			0x04
212 #define TSADCV2_INT_EN				0x08
213 #define TSADCV2_INT_PD				0x0c
214 #define TSADCV3_AUTO_SRC_CON			0x0c
215 #define TSADCV3_HT_INT_EN			0x14
216 #define TSADCV3_HSHUT_GPIO_INT_EN		0x18
217 #define TSADCV3_HSHUT_CRU_INT_EN		0x1c
218 #define TSADCV3_INT_PD				0x24
219 #define TSADCV3_HSHUT_PD			0x28
220 #define TSADCV2_DATA(chn)			(0x20 + (chn) * 0x04)
221 #define TSADCV2_COMP_INT(chn)		        (0x30 + (chn) * 0x04)
222 #define TSADCV2_COMP_SHUT(chn)		        (0x40 + (chn) * 0x04)
223 #define TSADCV3_DATA(chn)			(0x2c + (chn) * 0x04)
224 #define TSADCV3_COMP_INT(chn)		        (0x6c + (chn) * 0x04)
225 #define TSADCV3_COMP_SHUT(chn)		        (0x10c + (chn) * 0x04)
226 #define TSADCV2_HIGHT_INT_DEBOUNCE		0x60
227 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE		0x64
228 #define TSADCV3_HIGHT_INT_DEBOUNCE		0x14c
229 #define TSADCV3_HIGHT_TSHUT_DEBOUNCE		0x150
230 #define TSADCV2_AUTO_PERIOD			0x68
231 #define TSADCV2_AUTO_PERIOD_HT			0x6c
232 #define TSADCV3_AUTO_PERIOD			0x154
233 #define TSADCV3_AUTO_PERIOD_HT			0x158
234 #define TSADCV9_Q_MAX				0x210
235 #define TSADCV9_FLOW_CON			0x218
237 #define TSADCV2_AUTO_EN				BIT(0)
255 #define TSADCV4_INT_PD_CLEAR_MASK		0xffffffff
257 #define TSADCV2_DATA_MASK			0xfff
258 #define TSADCV3_DATA_MASK			0x3ff
259 #define TSADCV4_DATA_MASK			0x1ff
260 #define TSADCV5_DATA_MASK			0x7ff
276 #define TSADCV3_Q_MAX_VAL			0x7ff /* 11bit 2047 */
277 #define TSADCV12_Q_MAX_VAL			0xfff /* 12bit 4095 */
279 #define TSADCV2_USER_INTER_PD_SOC		0x340 /* 13 clocks */
280 #define TSADCV5_USER_INTER_PD_SOC		0xfc0 /* 97us, at least 90us */
282 #define TSADCV9_AUTO_SRC			(0x10001 << 0)
283 #define TSADCV9_PD_MODE				(0x10001 << 4)
284 #define TSADCV9_Q_MAX_VAL			(0xffff0400 << 0)
286 #define GRF_SARADC_TESTBIT			0x0e644
287 #define GRF_TSADC_TESTBIT_L			0x0e648
288 #define GRF_TSADC_TESTBIT_H			0x0e64c
290 #define PX30_GRF_SOC_CON0			0x0400
291 #define PX30_GRF_SOC_CON2			0x0408
293 #define RK1808_BUS_GRF_SOC_CON0			0x0400
295 #define RK3528_GRF_TSADC_CON			0x40030
297 #define RK3562_GRF_TSADC_CON			0x0580
299 #define RK3568_GRF_TSADC_CON			0x0600
300 #define RK3568_GRF_TSADC_ANA_REG0		(0x10001 << 0)
301 #define RK3568_GRF_TSADC_ANA_REG1		(0x10001 << 1)
302 #define RK3568_GRF_TSADC_ANA_REG2		(0x10001 << 2)
303 #define RK3568_GRF_TSADC_TSEN			(0x10001 << 8)
305 #define RV1106_VOGRF_TSADC_CON			0x6000C
306 #define RV1106_VOGRF_TSADC_TSEN			(0x10001 << 8)
307 #define RV1106_VOGRF_TSADC_ANA			(0xff0007 << 0)
309 #define RV1126_GRF0_TSADC_CON			0x0100
311 #define RV1126_GRF0_TSADC_TRM			(0xff0077 << 0)
312 #define RV1126_GRF0_TSADC_SHUT_2CRU		(0x30003 << 10)
313 #define RV1126_GRF0_TSADC_SHUT_2GPIO		(0x70007 << 12)
315 #define GRF_SARADC_TESTBIT_ON			(0x10001 << 2)
316 #define GRF_TSADC_TESTBIT_H_ON			(0x10001 << 2)
317 #define GRF_TSADC_BANDGAP_CHOPPER_EN		(0x10001 << 2)
318 #define GRF_TSADC_VCM_EN_L			(0x10001 << 7)
319 #define GRF_TSADC_VCM_EN_H			(0x10001 << 7)
321 #define GRF_CON_TSADC_CH_INV			(0x10001 << 1)
322 #define PX30S_TSADC_TDC_MODE			(0x10001 << 4)
323 #define PX30S_TSADC_TRIM			(0xf0007 << 0)
346 	{0, MIN_TEMP},
357 	{0, MIN_TEMP},
367 	{436, 0},
398 	{0, MIN_TEMP},
408 	{3519, 0},
439 	{0, MIN_TEMP},
449 	{629, 0},
490 	{3728, 0},
519 	{0, MAX_TEMP},
523 	{0, MIN_TEMP},
532 	{368, 0},
565 	{0, MIN_TEMP},
575 	{122, 0},
606 	{0, MIN_TEMP},
616 	{470, 0},
647 	{0, MIN_TEMP},
657 	{1486, 0},
688 	{0, MIN_TEMP},
698 	{1487, 0},
729 	{0, MIN_TEMP},
739 	{1856, 0},
770 	{0, MIN_TEMP},
791 	low = 0;  in rk_tsadcv2_temp_to_code()
848 		return 0;  in rk_tsadcv2_code_to_temp()
904 	return 0;  in rk_tsadcv2_code_to_temp()
911  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
929 		writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv2_initialize()
932 		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv2_initialize()
948  * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
1003 		writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv3_initialize()
1006 		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv3_initialize()
1021 		writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv5_initialize()
1024 		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv5_initialize()
1065 		writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv7_initialize()
1068 		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,  in rk_tsadcv7_initialize()
1325 		return 0;  in rk_tsadcv2_alarm_temp()
1340 	return 0;  in rk_tsadcv2_alarm_temp()
1357 		return 0;  in rk_tsadcv3_alarm_temp()
1367 	return 0;  in rk_tsadcv3_alarm_temp()
1386 	return 0;  in rk_tsadcv2_tshut_temp()
1405 	return 0;  in rk_tsadcv3_tshut_temp()
1508 	if (error < 0) {  in rk_tsadcv1_set_clk_rate()
1516 	return 0;  in rk_tsadcv1_set_clk_rate()
1520 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1544 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1568 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1589 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1613 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1639 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1663 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1712 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1736 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1762 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1785 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1810 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1835 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1860 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1884 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1910 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1938 	.chn_id = {0, 1, 2, 3, 4, 5, 6},
2085 	for (i = 0; i < thermal->chip->chn_num; i++)  in rockchip_thermal_alarm_irq_thread()
2160 	*value = buf[0];  in rockchip_get_efuse_value()
2164 	return 0;  in rockchip_get_efuse_value()
2173 	int trim_base = 0, trim_base_frac = 0, trim_l = 0, trim_h = 0;  in rockchip_get_trim_configure()
2178 		return 0;  in rockchip_get_trim_configure()
2195 			return 0;  in rockchip_get_trim_configure()
2200 		for (i = 0; i < thermal->chip->chn_num; i++) {  in rockchip_get_trim_configure()
2238 	return 0;  in rockchip_get_trim_configure()
2259 	for (i = 0; i < thermal->chip->chn_num; i++)  in rockchip_configure_from_dt()
2304 	return 0;  in rockchip_configure_from_dt()
2336 	return 0;  in rockchip_thermal_register_sensor()
2360 	for (i = 0; i < thermal->chip->chn_num; i++) {  in rockchip_dump_temperature()
2372 			       32, 4, thermal->regs, 0x88, false);  in rockchip_dump_temperature()
2401 	irq = platform_get_irq(pdev, 0);  in rockchip_thermal_probe()
2402 	if (irq < 0)  in rockchip_thermal_probe()
2420 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in rockchip_thermal_probe()
2479 	for (i = 0; i < thermal->chip->chn_num; i++) {  in rockchip_thermal_probe()
2506 	for (i = 0; i < thermal->chip->chn_num; i++) {  in rockchip_thermal_probe()
2522 	return 0;  in rockchip_thermal_probe()
2535 	for (i = 0; i < thermal->chip->chn_num; i++) {  in rockchip_thermal_remove()
2546 	return 0;  in rockchip_thermal_remove()
2554 	for (i = 0; i < thermal->chip->chn_num; i++) {  in rockchip_thermal_shutdown()
2571 	for (i = 0; i < thermal->chip->chn_num; i++)  in rockchip_thermal_suspend()
2581 	return 0;  in rockchip_thermal_suspend()
2602 	for (i = 0; i < thermal->chip->chn_num; i++) {  in rockchip_thermal_resume()
2622 	for (i = 0; i < thermal->chip->chn_num; i++)  in rockchip_thermal_resume()
2628 	return 0;  in rockchip_thermal_resume()