52 	u8 xf;		/* Crystal frequency value for PMU control */  member
58 	{ .freq = 12000, .xf =  1, .wb_int = 73, .wb_frac = 349525, },
59 	{ .freq = 13000, .xf =  2, .wb_int = 67, .wb_frac = 725937, },
60 	{ .freq = 14400, .xf =  3, .wb_int = 61, .wb_frac = 116508, },
61 	{ .freq = 15360, .xf =  4, .wb_int = 57, .wb_frac = 305834, },
62 	{ .freq = 16200, .xf =  5, .wb_int = 54, .wb_frac = 336579, },
63 	{ .freq = 16800, .xf =  6, .wb_int = 52, .wb_frac = 399457, },
64 	{ .freq = 19200, .xf =  7, .wb_int = 45, .wb_frac = 873813, },
65 	{ .freq = 19800, .xf =  8, .wb_int = 44, .wb_frac = 466033, },
66 	{ .freq = 20000, .xf =  9, .wb_int = 44, .wb_frac = 0,      },
67 	{ .freq = 25000, .xf = 10, .wb_int = 70, .wb_frac = 419430, },
68 	{ .freq = 26000, .xf = 11, .wb_int = 67, .wb_frac = 725937, },
69 	{ .freq = 30000, .xf = 12, .wb_int = 58, .wb_frac = 699050, },
70 	{ .freq = 38400, .xf = 13, .wb_int = 45, .wb_frac = 873813, },
71 	{ .freq = 40000, .xf = 14, .wb_int = 45, .wb_frac = 0,      },
80 	for (i = 0; i < ARRAY_SIZE(pmu0_plltab); i++) {  in pmu0_plltab_find_entry()
108 	if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) {  in ssb_pmu0_pllinit_r0()
118 	case 0x4328:  in ssb_pmu0_pllinit_r0()
124 	case 0x5354:  in ssb_pmu0_pllinit_r0()
143 	/* Set PDIV in PLL control 0. */  in ssb_pmu0_pllinit_r0()
157 	if (e->wb_frac == 0)  in ssb_pmu0_pllinit_r0()
173 	pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ;  in ssb_pmu0_pllinit_r0()
179 	u8 xf;		/* Crystal frequency value for PMU control */  member
187 	{ .freq = 12000, .xf =  1, .p1div = 3, .p2div = 22, .ndiv_int =  0x9, .ndiv_frac = 0xFFFFEF, },
188 	{ .freq = 13000, .xf =  2, .p1div = 1, .p2div =  6, .ndiv_int =  0xb, .ndiv_frac = 0x483483, },
189 	{ .freq = 14400, .xf =  3, .p1div = 1, .p2div = 10, .ndiv_int =  0xa, .ndiv_frac = 0x1C71C7, },
190 	{ .freq = 15360, .xf =  4, .p1div = 1, .p2div =  5, .ndiv_int =  0xb, .ndiv_frac = 0x755555, },
191 	{ .freq = 16200, .xf =  5, .p1div = 1, .p2div = 10, .ndiv_int =  0x5, .ndiv_frac = 0x6E9E06, },
192 	{ .freq = 16800, .xf =  6, .p1div = 1, .p2div = 10, .ndiv_int =  0x5, .ndiv_frac = 0x3CF3CF, },
193 	{ .freq = 19200, .xf =  7, .p1div = 1, .p2div =  9, .ndiv_int =  0x5, .ndiv_frac = 0x17B425, },
194 	{ .freq = 19800, .xf =  8, .p1div = 1, .p2div = 11, .ndiv_int =  0x4, .ndiv_frac = 0xA57EB,  },
195 	{ .freq = 20000, .xf =  9, .p1div = 1, .p2div = 11, .ndiv_int =  0x4, .ndiv_frac = 0,        },
196 	{ .freq = 24000, .xf = 10, .p1div = 3, .p2div = 11, .ndiv_int =  0xa, .ndiv_frac = 0,        },
197 	{ .freq = 25000, .xf = 11, .p1div = 5, .p2div = 16, .ndiv_int =  0xb, .ndiv_frac = 0,        },
198 	{ .freq = 26000, .xf = 12, .p1div = 1, .p2div =  2, .ndiv_int = 0x10, .ndiv_frac = 0xEC4EC4, },
199 	{ .freq = 30000, .xf = 13, .p1div = 3, .p2div =  8, .ndiv_int =  0xb, .ndiv_frac = 0,        },
200 	{ .freq = 38400, .xf = 14, .p1div = 1, .p2div =  5, .ndiv_int =  0x4, .ndiv_frac = 0x955555, },
201 	{ .freq = 40000, .xf = 15, .p1div = 1, .p2div =  2, .ndiv_int =  0xb, .ndiv_frac = 0,        },
211 	for (i = 0; i < ARRAY_SIZE(pmu1_plltab); i++) {  in pmu1_plltab_find_entry()
226 	u32 buffer_strength = 0;  in ssb_pmu1_pllinit_r0()
230 	if (bus->chip_id == 0x4312) {  in ssb_pmu1_pllinit_r0()
247 	if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) {  in ssb_pmu1_pllinit_r0()
257 	case 0x4325:  in ssb_pmu1_pllinit_r0()
265 		buffer_strength = 0x222222;  in ssb_pmu1_pllinit_r0()
313 	pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ;  in ssb_pmu1_pllinit_r0()
320 	u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */  in ssb_pmu_pll_init()
325 		if (bcm47xx_nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)  in ssb_pmu_pll_init()
326 			crystalfreq = simple_strtoul(buf, NULL, 0);  in ssb_pmu_pll_init()
331 	case 0x4312:  in ssb_pmu_pll_init()
332 	case 0x4325:  in ssb_pmu_pll_init()
335 	case 0x4328:  in ssb_pmu_pll_init()
338 	case 0x5354:  in ssb_pmu_pll_init()
339 		if (crystalfreq == 0)  in ssb_pmu_pll_init()
343 	case 0x4322:  in ssb_pmu_pll_init()
345 			chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);  in ssb_pmu_pll_init()
346 			chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);  in ssb_pmu_pll_init()
375 	{ .resource = SSB_PMURES_4328_EXT_SWITCHER_PWM,		.updown = 0x0101, },
376 	{ .resource = SSB_PMURES_4328_BB_SWITCHER_PWM,		.updown = 0x1F01, },
377 	{ .resource = SSB_PMURES_4328_BB_SWITCHER_BURST,	.updown = 0x010F, },
378 	{ .resource = SSB_PMURES_4328_BB_EXT_SWITCHER_BURST,	.updown = 0x0101, },
379 	{ .resource = SSB_PMURES_4328_ILP_REQUEST,		.updown = 0x0202, },
380 	{ .resource = SSB_PMURES_4328_RADIO_SWITCHER_PWM,	.updown = 0x0F01, },
381 	{ .resource = SSB_PMURES_4328_RADIO_SWITCHER_BURST,	.updown = 0x0F01, },
382 	{ .resource = SSB_PMURES_4328_ROM_SWITCH,		.updown = 0x0101, },
383 	{ .resource = SSB_PMURES_4328_PA_REF_LDO,		.updown = 0x0F01, },
384 	{ .resource = SSB_PMURES_4328_RADIO_LDO,		.updown = 0x0F01, },
385 	{ .resource = SSB_PMURES_4328_AFE_LDO,			.updown = 0x0F01, },
386 	{ .resource = SSB_PMURES_4328_PLL_LDO,			.updown = 0x0F01, },
387 	{ .resource = SSB_PMURES_4328_BG_FILTBYP,		.updown = 0x0101, },
388 	{ .resource = SSB_PMURES_4328_TX_FILTBYP,		.updown = 0x0101, },
389 	{ .resource = SSB_PMURES_4328_RX_FILTBYP,		.updown = 0x0101, },
390 	{ .resource = SSB_PMURES_4328_XTAL_PU,			.updown = 0x0101, },
391 	{ .resource = SSB_PMURES_4328_XTAL_EN,			.updown = 0xA001, },
392 	{ .resource = SSB_PMURES_4328_BB_PLL_FILTBYP,		.updown = 0x0101, },
393 	{ .resource = SSB_PMURES_4328_RF_PLL_FILTBYP,		.updown = 0x0101, },
394 	{ .resource = SSB_PMURES_4328_BB_PLL_PU,		.updown = 0x0701, },
408 	{ .resource = SSB_PMURES_4325_XTAL_PU,			.updown = 0x1501, },
426 	u32 min_msk = 0, max_msk = 0;  in ssb_pmu_resources_init()
429 	unsigned int updown_tab_size = 0;  in ssb_pmu_resources_init()
431 	unsigned int depend_tab_size = 0;  in ssb_pmu_resources_init()
434 	case 0x4312:  in ssb_pmu_resources_init()
435 		 min_msk = 0xCBB;  in ssb_pmu_resources_init()
437 	case 0x4322:  in ssb_pmu_resources_init()
440 		 * min_msk = 0xCBB  in ssb_pmu_resources_init()
441 		 * max_msk = 0x7FFFF  in ssb_pmu_resources_init()
444 	case 0x4325:  in ssb_pmu_resources_init()
452 		max_msk = 0xFFFFF;  in ssb_pmu_resources_init()
458 	case 0x4328:  in ssb_pmu_resources_init()
463 		max_msk = 0xFFFFF;  in ssb_pmu_resources_init()
469 	case 0x5354:  in ssb_pmu_resources_init()
471 		max_msk = 0xFFFFF;  in ssb_pmu_resources_init()
479 		for (i = 0; i < updown_tab_size; i++) {  in ssb_pmu_resources_init()
487 		for (i = 0; i < depend_tab_size; i++) {  in ssb_pmu_resources_init()
527 	dev_dbg(cc->dev->dev, "Found rev %u PMU (capabilities 0x%08X)\n",  in ssb_pmu_init()
547 	case 0x4328:  in ssb_pmu_set_ldo_voltage()
548 	case 0x5354:  in ssb_pmu_set_ldo_voltage()
553 			mask = 0xF;  in ssb_pmu_set_ldo_voltage()
558 			mask = 0xF;  in ssb_pmu_set_ldo_voltage()
563 			mask = 0xF;  in ssb_pmu_set_ldo_voltage()
568 			mask = 0x3F;  in ssb_pmu_set_ldo_voltage()
575 	case 0x4312:  in ssb_pmu_set_ldo_voltage()
578 		addr = 0;  in ssb_pmu_set_ldo_voltage()
580 		mask = 0x3F;  in ssb_pmu_set_ldo_voltage()
596 	case 0x4312:  in ssb_pmu_set_ldo_paref()
599 	case 0x4328:  in ssb_pmu_set_ldo_paref()
602 	case 0x5354:  in ssb_pmu_set_ldo_paref()
636 	case 0x5354:  in ssb_pmu_get_alp_clock()
641 		return 0;  in ssb_pmu_get_alp_clock()
650 	case 0x5354:  in ssb_pmu_get_cpu_clock()
656 		return 0;  in ssb_pmu_get_cpu_clock()
665 	case 0x5354:  in ssb_pmu_get_controlclock()
670 		return 0;  in ssb_pmu_get_controlclock()
676 	u32 pmu_ctl = 0;  in ssb_pmu_spuravoid_pllupdate()
679 	case 0x4322:  in ssb_pmu_spuravoid_pllupdate()
680 		ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070);  in ssb_pmu_spuravoid_pllupdate()
681 		ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a);  in ssb_pmu_spuravoid_pllupdate()
682 		ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854);  in ssb_pmu_spuravoid_pllupdate()
684 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828);  in ssb_pmu_spuravoid_pllupdate()
686 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828);  in ssb_pmu_spuravoid_pllupdate()
691 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11500008);  in ssb_pmu_spuravoid_pllupdate()
692 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0C000C06);  in ssb_pmu_spuravoid_pllupdate()
693 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x0F600a08);  in ssb_pmu_spuravoid_pllupdate()
694 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);  in ssb_pmu_spuravoid_pllupdate()
695 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x2001E920);  in ssb_pmu_spuravoid_pllupdate()
696 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888815);  in ssb_pmu_spuravoid_pllupdate()
698 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100008);  in ssb_pmu_spuravoid_pllupdate()
699 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0c000c06);  in ssb_pmu_spuravoid_pllupdate()
700 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x03000a08);  in ssb_pmu_spuravoid_pllupdate()
701 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);  in ssb_pmu_spuravoid_pllupdate()
702 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x200005c0);  in ssb_pmu_spuravoid_pllupdate()
703 			ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888855);  in ssb_pmu_spuravoid_pllupdate()
709 			"Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",  in ssb_pmu_spuravoid_pllupdate()