154 static inline void zynq_qspi_write(struct zynq_qspi *xqspi, u32 offset,  in zynq_qspi_write()  function
185 	zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0);  in zynq_qspi_init_hw()
186 	zynq_qspi_write(xqspi, ZYNQ_QSPI_IDIS_OFFSET, ZYNQ_QSPI_IXR_ALL_MASK);  in zynq_qspi_init_hw()
194 	zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, config_reg);  in zynq_qspi_init_hw()
201 	zynq_qspi_write(xqspi, ZYNQ_QSPI_STATUS_OFFSET, ZYNQ_QSPI_IXR_ALL_MASK);  in zynq_qspi_init_hw()
214 	zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);  in zynq_qspi_init_hw()
216 	zynq_qspi_write(xqspi, ZYNQ_QSPI_RX_THRESH_OFFSET,  in zynq_qspi_init_hw()
218 	zynq_qspi_write(xqspi, ZYNQ_QSPI_TX_THRESH_OFFSET,  in zynq_qspi_init_hw()
221 	zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET,  in zynq_qspi_init_hw()
282 	zynq_qspi_write(xqspi, offset[size - 1], data);  in zynq_qspi_txfifo_op()
304 		zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, config_reg);  in zynq_qspi_chipselect()
314 	zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);  in zynq_qspi_chipselect()
364 	zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);  in zynq_qspi_config_op()
388 	zynq_qspi_write(qspi, ZYNQ_QSPI_ENABLE_OFFSET,  in zynq_qspi_setup_op()
480 	zynq_qspi_write(xqspi, ZYNQ_QSPI_STATUS_OFFSET, intr_status);  in zynq_qspi_irq()
502 				zynq_qspi_write(xqspi,  in zynq_qspi_irq()
546 		zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,  in zynq_qspi_exec_mem_op()
564 		zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,  in zynq_qspi_exec_mem_op()
583 		zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,  in zynq_qspi_exec_mem_op()
607 		zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,  in zynq_qspi_exec_mem_op()
748 	zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0);  in zynq_qspi_remove()