Lines Matching refs:tspi
227 static inline u32 tegra_spi_readl(struct tegra_spi_data *tspi, in tegra_spi_readl() argument
230 return readl(tspi->base + reg); in tegra_spi_readl()
233 static inline void tegra_spi_writel(struct tegra_spi_data *tspi, in tegra_spi_writel() argument
236 writel(val, tspi->base + reg); in tegra_spi_writel()
240 readl(tspi->base + SPI_COMMAND1); in tegra_spi_writel()
243 static void tegra_spi_clear_status(struct tegra_spi_data *tspi) in tegra_spi_clear_status() argument
248 val = tegra_spi_readl(tspi, SPI_TRANS_STATUS); in tegra_spi_clear_status()
249 tegra_spi_writel(tspi, val, SPI_TRANS_STATUS); in tegra_spi_clear_status()
252 val = tegra_spi_readl(tspi, SPI_FIFO_STATUS); in tegra_spi_clear_status()
254 tegra_spi_writel(tspi, SPI_ERR | SPI_FIFO_ERROR, in tegra_spi_clear_status()
259 struct spi_device *spi, struct tegra_spi_data *tspi, in tegra_spi_calculate_curr_xfer_param() argument
262 unsigned remain_len = t->len - tspi->cur_pos; in tegra_spi_calculate_curr_xfer_param()
268 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); in tegra_spi_calculate_curr_xfer_param()
272 tspi->is_packed = true; in tegra_spi_calculate_curr_xfer_param()
273 tspi->words_per_32bit = 32/bits_per_word; in tegra_spi_calculate_curr_xfer_param()
275 tspi->is_packed = false; in tegra_spi_calculate_curr_xfer_param()
276 tspi->words_per_32bit = 1; in tegra_spi_calculate_curr_xfer_param()
279 if (tspi->is_packed) { in tegra_spi_calculate_curr_xfer_param()
280 max_len = min(remain_len, tspi->max_buf_size); in tegra_spi_calculate_curr_xfer_param()
281 tspi->curr_dma_words = max_len/tspi->bytes_per_word; in tegra_spi_calculate_curr_xfer_param()
284 max_word = (remain_len - 1) / tspi->bytes_per_word + 1; in tegra_spi_calculate_curr_xfer_param()
285 max_word = min(max_word, tspi->max_buf_size/4); in tegra_spi_calculate_curr_xfer_param()
286 tspi->curr_dma_words = max_word; in tegra_spi_calculate_curr_xfer_param()
293 struct tegra_spi_data *tspi, struct spi_transfer *t) in tegra_spi_fill_tx_fifo_from_client_txbuf() argument
302 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; in tegra_spi_fill_tx_fifo_from_client_txbuf()
304 fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS); in tegra_spi_fill_tx_fifo_from_client_txbuf()
307 if (tspi->is_packed) { in tegra_spi_fill_tx_fifo_from_client_txbuf()
308 fifo_words_left = tx_empty_count * tspi->words_per_32bit; in tegra_spi_fill_tx_fifo_from_client_txbuf()
309 written_words = min(fifo_words_left, tspi->curr_dma_words); in tegra_spi_fill_tx_fifo_from_client_txbuf()
310 nbytes = written_words * tspi->bytes_per_word; in tegra_spi_fill_tx_fifo_from_client_txbuf()
317 tegra_spi_writel(tspi, x, SPI_TX_FIFO); in tegra_spi_fill_tx_fifo_from_client_txbuf()
320 tspi->cur_tx_pos += written_words * tspi->bytes_per_word; in tegra_spi_fill_tx_fifo_from_client_txbuf()
323 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count); in tegra_spi_fill_tx_fifo_from_client_txbuf()
325 nbytes = written_words * tspi->bytes_per_word; in tegra_spi_fill_tx_fifo_from_client_txbuf()
326 if (nbytes > t->len - tspi->cur_pos) in tegra_spi_fill_tx_fifo_from_client_txbuf()
327 nbytes = t->len - tspi->cur_pos; in tegra_spi_fill_tx_fifo_from_client_txbuf()
332 for (i = 0; nbytes && (i < tspi->bytes_per_word); in tegra_spi_fill_tx_fifo_from_client_txbuf()
335 tegra_spi_writel(tspi, x, SPI_TX_FIFO); in tegra_spi_fill_tx_fifo_from_client_txbuf()
338 tspi->cur_tx_pos += write_bytes; in tegra_spi_fill_tx_fifo_from_client_txbuf()
345 struct tegra_spi_data *tspi, struct spi_transfer *t) in tegra_spi_read_rx_fifo_to_client_rxbuf() argument
352 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos; in tegra_spi_read_rx_fifo_to_client_rxbuf()
354 fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS); in tegra_spi_read_rx_fifo_to_client_rxbuf()
356 if (tspi->is_packed) { in tegra_spi_read_rx_fifo_to_client_rxbuf()
357 len = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_read_rx_fifo_to_client_rxbuf()
359 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO); in tegra_spi_read_rx_fifo_to_client_rxbuf()
364 read_words += tspi->curr_dma_words; in tegra_spi_read_rx_fifo_to_client_rxbuf()
365 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_read_rx_fifo_to_client_rxbuf()
368 u8 bytes_per_word = tspi->bytes_per_word; in tegra_spi_read_rx_fifo_to_client_rxbuf()
372 if (len > t->len - tspi->cur_pos) in tegra_spi_read_rx_fifo_to_client_rxbuf()
373 len = t->len - tspi->cur_pos; in tegra_spi_read_rx_fifo_to_client_rxbuf()
376 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask; in tegra_spi_read_rx_fifo_to_client_rxbuf()
382 tspi->cur_rx_pos += read_bytes; in tegra_spi_read_rx_fifo_to_client_rxbuf()
389 struct tegra_spi_data *tspi, struct spi_transfer *t) in tegra_spi_copy_client_txbuf_to_spi_txbuf() argument
392 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys, in tegra_spi_copy_client_txbuf_to_spi_txbuf()
393 tspi->dma_buf_size, DMA_TO_DEVICE); in tegra_spi_copy_client_txbuf_to_spi_txbuf()
395 if (tspi->is_packed) { in tegra_spi_copy_client_txbuf_to_spi_txbuf()
396 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
398 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len); in tegra_spi_copy_client_txbuf_to_spi_txbuf()
399 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
403 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
404 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
407 if (consume > t->len - tspi->cur_pos) in tegra_spi_copy_client_txbuf_to_spi_txbuf()
408 consume = t->len - tspi->cur_pos; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
410 for (count = 0; count < tspi->curr_dma_words; count++) { in tegra_spi_copy_client_txbuf_to_spi_txbuf()
413 for (i = 0; consume && (i < tspi->bytes_per_word); in tegra_spi_copy_client_txbuf_to_spi_txbuf()
416 tspi->tx_dma_buf[count] = x; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
419 tspi->cur_tx_pos += write_bytes; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
423 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys, in tegra_spi_copy_client_txbuf_to_spi_txbuf()
424 tspi->dma_buf_size, DMA_TO_DEVICE); in tegra_spi_copy_client_txbuf_to_spi_txbuf()
428 struct tegra_spi_data *tspi, struct spi_transfer *t) in tegra_spi_copy_spi_rxbuf_to_client_rxbuf() argument
431 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys, in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
432 tspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
434 if (tspi->is_packed) { in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
435 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
437 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len); in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
438 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
442 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
444 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
447 if (consume > t->len - tspi->cur_pos) in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
448 consume = t->len - tspi->cur_pos; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
450 for (count = 0; count < tspi->curr_dma_words; count++) { in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
451 u32 x = tspi->rx_dma_buf[count] & rx_mask; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
453 for (i = 0; consume && (i < tspi->bytes_per_word); in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
458 tspi->cur_rx_pos += read_bytes; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
462 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
463 tspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
473 static int tegra_spi_start_tx_dma(struct tegra_spi_data *tspi, int len) in tegra_spi_start_tx_dma() argument
475 reinit_completion(&tspi->tx_dma_complete); in tegra_spi_start_tx_dma()
476 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan, in tegra_spi_start_tx_dma()
477 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV, in tegra_spi_start_tx_dma()
479 if (!tspi->tx_dma_desc) { in tegra_spi_start_tx_dma()
480 dev_err(tspi->dev, "Not able to get desc for Tx\n"); in tegra_spi_start_tx_dma()
484 tspi->tx_dma_desc->callback = tegra_spi_dma_complete; in tegra_spi_start_tx_dma()
485 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete; in tegra_spi_start_tx_dma()
487 dmaengine_submit(tspi->tx_dma_desc); in tegra_spi_start_tx_dma()
488 dma_async_issue_pending(tspi->tx_dma_chan); in tegra_spi_start_tx_dma()
492 static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len) in tegra_spi_start_rx_dma() argument
494 reinit_completion(&tspi->rx_dma_complete); in tegra_spi_start_rx_dma()
495 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan, in tegra_spi_start_rx_dma()
496 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM, in tegra_spi_start_rx_dma()
498 if (!tspi->rx_dma_desc) { in tegra_spi_start_rx_dma()
499 dev_err(tspi->dev, "Not able to get desc for Rx\n"); in tegra_spi_start_rx_dma()
503 tspi->rx_dma_desc->callback = tegra_spi_dma_complete; in tegra_spi_start_rx_dma()
504 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete; in tegra_spi_start_rx_dma()
506 dmaengine_submit(tspi->rx_dma_desc); in tegra_spi_start_rx_dma()
507 dma_async_issue_pending(tspi->rx_dma_chan); in tegra_spi_start_rx_dma()
511 static int tegra_spi_flush_fifos(struct tegra_spi_data *tspi) in tegra_spi_flush_fifos() argument
516 status = tegra_spi_readl(tspi, SPI_FIFO_STATUS); in tegra_spi_flush_fifos()
519 tegra_spi_writel(tspi, status, SPI_FIFO_STATUS); in tegra_spi_flush_fifos()
521 status = tegra_spi_readl(tspi, SPI_FIFO_STATUS); in tegra_spi_flush_fifos()
523 dev_err(tspi->dev, in tegra_spi_flush_fifos()
536 struct tegra_spi_data *tspi, struct spi_transfer *t) in tegra_spi_start_dma_based_transfer() argument
544 val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1); in tegra_spi_start_dma_based_transfer()
545 tegra_spi_writel(tspi, val, SPI_DMA_BLK); in tegra_spi_start_dma_based_transfer()
547 if (tspi->is_packed) in tegra_spi_start_dma_based_transfer()
548 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word, in tegra_spi_start_dma_based_transfer()
551 len = tspi->curr_dma_words * 4; in tegra_spi_start_dma_based_transfer()
565 if (!tspi->soc_data->has_intr_mask_reg) { in tegra_spi_start_dma_based_transfer()
566 if (tspi->cur_direction & DATA_DIR_TX) in tegra_spi_start_dma_based_transfer()
569 if (tspi->cur_direction & DATA_DIR_RX) in tegra_spi_start_dma_based_transfer()
573 tegra_spi_writel(tspi, val, SPI_DMA_CTL); in tegra_spi_start_dma_based_transfer()
574 tspi->dma_control_reg = val; in tegra_spi_start_dma_based_transfer()
577 if (tspi->cur_direction & DATA_DIR_TX) { in tegra_spi_start_dma_based_transfer()
578 dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO; in tegra_spi_start_dma_based_transfer()
581 ret = dmaengine_slave_config(tspi->tx_dma_chan, &dma_sconfig); in tegra_spi_start_dma_based_transfer()
583 dev_err(tspi->dev, in tegra_spi_start_dma_based_transfer()
588 tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t); in tegra_spi_start_dma_based_transfer()
589 ret = tegra_spi_start_tx_dma(tspi, len); in tegra_spi_start_dma_based_transfer()
591 dev_err(tspi->dev, in tegra_spi_start_dma_based_transfer()
597 if (tspi->cur_direction & DATA_DIR_RX) { in tegra_spi_start_dma_based_transfer()
598 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO; in tegra_spi_start_dma_based_transfer()
601 ret = dmaengine_slave_config(tspi->rx_dma_chan, &dma_sconfig); in tegra_spi_start_dma_based_transfer()
603 dev_err(tspi->dev, in tegra_spi_start_dma_based_transfer()
609 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, in tegra_spi_start_dma_based_transfer()
610 tspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_spi_start_dma_based_transfer()
612 ret = tegra_spi_start_rx_dma(tspi, len); in tegra_spi_start_dma_based_transfer()
614 dev_err(tspi->dev, in tegra_spi_start_dma_based_transfer()
616 if (tspi->cur_direction & DATA_DIR_TX) in tegra_spi_start_dma_based_transfer()
617 dmaengine_terminate_all(tspi->tx_dma_chan); in tegra_spi_start_dma_based_transfer()
621 tspi->is_curr_dma_xfer = true; in tegra_spi_start_dma_based_transfer()
622 tspi->dma_control_reg = val; in tegra_spi_start_dma_based_transfer()
625 tegra_spi_writel(tspi, val, SPI_DMA_CTL); in tegra_spi_start_dma_based_transfer()
630 struct tegra_spi_data *tspi, struct spi_transfer *t) in tegra_spi_start_cpu_based_transfer() argument
635 if (tspi->cur_direction & DATA_DIR_TX) in tegra_spi_start_cpu_based_transfer()
636 cur_words = tegra_spi_fill_tx_fifo_from_client_txbuf(tspi, t); in tegra_spi_start_cpu_based_transfer()
638 cur_words = tspi->curr_dma_words; in tegra_spi_start_cpu_based_transfer()
641 tegra_spi_writel(tspi, val, SPI_DMA_BLK); in tegra_spi_start_cpu_based_transfer()
644 if (tspi->cur_direction & DATA_DIR_TX) in tegra_spi_start_cpu_based_transfer()
647 if (tspi->cur_direction & DATA_DIR_RX) in tegra_spi_start_cpu_based_transfer()
650 tegra_spi_writel(tspi, val, SPI_DMA_CTL); in tegra_spi_start_cpu_based_transfer()
651 tspi->dma_control_reg = val; in tegra_spi_start_cpu_based_transfer()
653 tspi->is_curr_dma_xfer = false; in tegra_spi_start_cpu_based_transfer()
655 val = tspi->command1_reg; in tegra_spi_start_cpu_based_transfer()
657 tegra_spi_writel(tspi, val, SPI_COMMAND1); in tegra_spi_start_cpu_based_transfer()
661 static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi, in tegra_spi_init_dma_param() argument
668 dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx"); in tegra_spi_init_dma_param()
670 return dev_err_probe(tspi->dev, PTR_ERR(dma_chan), in tegra_spi_init_dma_param()
673 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, in tegra_spi_init_dma_param()
676 dev_err(tspi->dev, " Not able to allocate the dma buffer\n"); in tegra_spi_init_dma_param()
682 tspi->rx_dma_chan = dma_chan; in tegra_spi_init_dma_param()
683 tspi->rx_dma_buf = dma_buf; in tegra_spi_init_dma_param()
684 tspi->rx_dma_phys = dma_phys; in tegra_spi_init_dma_param()
686 tspi->tx_dma_chan = dma_chan; in tegra_spi_init_dma_param()
687 tspi->tx_dma_buf = dma_buf; in tegra_spi_init_dma_param()
688 tspi->tx_dma_phys = dma_phys; in tegra_spi_init_dma_param()
693 static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi, in tegra_spi_deinit_dma_param() argument
701 dma_buf = tspi->rx_dma_buf; in tegra_spi_deinit_dma_param()
702 dma_chan = tspi->rx_dma_chan; in tegra_spi_deinit_dma_param()
703 dma_phys = tspi->rx_dma_phys; in tegra_spi_deinit_dma_param()
704 tspi->rx_dma_chan = NULL; in tegra_spi_deinit_dma_param()
705 tspi->rx_dma_buf = NULL; in tegra_spi_deinit_dma_param()
707 dma_buf = tspi->tx_dma_buf; in tegra_spi_deinit_dma_param()
708 dma_chan = tspi->tx_dma_chan; in tegra_spi_deinit_dma_param()
709 dma_phys = tspi->tx_dma_phys; in tegra_spi_deinit_dma_param()
710 tspi->tx_dma_buf = NULL; in tegra_spi_deinit_dma_param()
711 tspi->tx_dma_chan = NULL; in tegra_spi_deinit_dma_param()
716 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); in tegra_spi_deinit_dma_param()
725 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); in tegra_spi_set_hw_cs_timing() local
749 spi_cs_timing = SPI_CS_SETUP_HOLD(tspi->spi_cs_timing1, in tegra_spi_set_hw_cs_timing()
752 if (tspi->spi_cs_timing1 != spi_cs_timing) { in tegra_spi_set_hw_cs_timing()
753 tspi->spi_cs_timing1 = spi_cs_timing; in tegra_spi_set_hw_cs_timing()
754 tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING1); in tegra_spi_set_hw_cs_timing()
762 spi_cs_timing = tspi->spi_cs_timing2; in tegra_spi_set_hw_cs_timing()
767 if (tspi->spi_cs_timing2 != spi_cs_timing) { in tegra_spi_set_hw_cs_timing()
768 tspi->spi_cs_timing2 = spi_cs_timing; in tegra_spi_set_hw_cs_timing()
769 tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING2); in tegra_spi_set_hw_cs_timing()
780 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); in tegra_spi_setup_transfer_one() local
788 if (speed != tspi->cur_speed) { in tegra_spi_setup_transfer_one()
789 clk_set_rate(tspi->clk, speed); in tegra_spi_setup_transfer_one()
790 tspi->cur_speed = speed; in tegra_spi_setup_transfer_one()
793 tspi->cur_spi = spi; in tegra_spi_setup_transfer_one()
794 tspi->cur_pos = 0; in tegra_spi_setup_transfer_one()
795 tspi->cur_rx_pos = 0; in tegra_spi_setup_transfer_one()
796 tspi->cur_tx_pos = 0; in tegra_spi_setup_transfer_one()
797 tspi->curr_xfer = t; in tegra_spi_setup_transfer_one()
800 tegra_spi_clear_status(tspi); in tegra_spi_setup_transfer_one()
802 command1 = tspi->def_command1_reg; in tegra_spi_setup_transfer_one()
826 if (tspi->cs_control) { in tegra_spi_setup_transfer_one()
827 if (tspi->cs_control != spi) in tegra_spi_setup_transfer_one()
828 tegra_spi_writel(tspi, command1, SPI_COMMAND1); in tegra_spi_setup_transfer_one()
829 tspi->cs_control = NULL; in tegra_spi_setup_transfer_one()
831 tegra_spi_writel(tspi, command1, SPI_COMMAND1); in tegra_spi_setup_transfer_one()
838 tspi->use_hw_based_cs = true; in tegra_spi_setup_transfer_one()
841 tspi->use_hw_based_cs = false; in tegra_spi_setup_transfer_one()
849 if (tspi->last_used_cs != spi->chip_select) { in tegra_spi_setup_transfer_one()
856 if (command2 != tspi->def_command2_reg) in tegra_spi_setup_transfer_one()
857 tegra_spi_writel(tspi, command2, SPI_COMMAND2); in tegra_spi_setup_transfer_one()
858 tspi->last_used_cs = spi->chip_select; in tegra_spi_setup_transfer_one()
862 command1 = tspi->command1_reg; in tegra_spi_setup_transfer_one()
873 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); in tegra_spi_start_transfer_one() local
877 total_fifo_words = tegra_spi_calculate_curr_xfer_param(spi, tspi, t); in tegra_spi_start_transfer_one()
884 if (tspi->is_packed) in tegra_spi_start_transfer_one()
890 tspi->cur_direction = 0; in tegra_spi_start_transfer_one()
893 tspi->cur_direction |= DATA_DIR_RX; in tegra_spi_start_transfer_one()
897 tspi->cur_direction |= DATA_DIR_TX; in tegra_spi_start_transfer_one()
900 tegra_spi_writel(tspi, command1, SPI_COMMAND1); in tegra_spi_start_transfer_one()
901 tspi->command1_reg = command1; in tegra_spi_start_transfer_one()
903 dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n", in tegra_spi_start_transfer_one()
904 tspi->def_command1_reg, (unsigned)command1); in tegra_spi_start_transfer_one()
906 ret = tegra_spi_flush_fifos(tspi); in tegra_spi_start_transfer_one()
910 ret = tegra_spi_start_dma_based_transfer(tspi, t); in tegra_spi_start_transfer_one()
912 ret = tegra_spi_start_cpu_based_transfer(tspi, t); in tegra_spi_start_transfer_one()
950 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); in tegra_spi_setup() local
967 ret = pm_runtime_get_sync(tspi->dev); in tegra_spi_setup()
969 pm_runtime_put_noidle(tspi->dev); in tegra_spi_setup()
970 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); in tegra_spi_setup()
976 if (tspi->soc_data->has_intr_mask_reg) { in tegra_spi_setup()
977 val = tegra_spi_readl(tspi, SPI_INTR_MASK); in tegra_spi_setup()
979 tegra_spi_writel(tspi, val, SPI_INTR_MASK); in tegra_spi_setup()
982 spin_lock_irqsave(&tspi->lock, flags); in tegra_spi_setup()
987 val = tspi->def_command1_reg; in tegra_spi_setup()
992 tspi->def_command1_reg = val; in tegra_spi_setup()
993 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); in tegra_spi_setup()
994 spin_unlock_irqrestore(&tspi->lock, flags); in tegra_spi_setup()
996 pm_runtime_put(tspi->dev); in tegra_spi_setup()
1002 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); in tegra_spi_transfer_end() local
1009 if (!tspi->use_hw_based_cs) { in tegra_spi_transfer_end()
1011 tspi->command1_reg |= SPI_CS_SW_VAL; in tegra_spi_transfer_end()
1013 tspi->command1_reg &= ~SPI_CS_SW_VAL; in tegra_spi_transfer_end()
1014 tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1); in tegra_spi_transfer_end()
1017 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); in tegra_spi_transfer_end()
1020 static void tegra_spi_dump_regs(struct tegra_spi_data *tspi) in tegra_spi_dump_regs() argument
1022 dev_dbg(tspi->dev, "============ SPI REGISTER DUMP ============\n"); in tegra_spi_dump_regs()
1023 dev_dbg(tspi->dev, "Command1: 0x%08x | Command2: 0x%08x\n", in tegra_spi_dump_regs()
1024 tegra_spi_readl(tspi, SPI_COMMAND1), in tegra_spi_dump_regs()
1025 tegra_spi_readl(tspi, SPI_COMMAND2)); in tegra_spi_dump_regs()
1026 dev_dbg(tspi->dev, "DMA_CTL: 0x%08x | DMA_BLK: 0x%08x\n", in tegra_spi_dump_regs()
1027 tegra_spi_readl(tspi, SPI_DMA_CTL), in tegra_spi_dump_regs()
1028 tegra_spi_readl(tspi, SPI_DMA_BLK)); in tegra_spi_dump_regs()
1029 dev_dbg(tspi->dev, "TRANS_STAT: 0x%08x | FIFO_STATUS: 0x%08x\n", in tegra_spi_dump_regs()
1030 tegra_spi_readl(tspi, SPI_TRANS_STATUS), in tegra_spi_dump_regs()
1031 tegra_spi_readl(tspi, SPI_FIFO_STATUS)); in tegra_spi_dump_regs()
1038 struct tegra_spi_data *tspi = spi_master_get_devdata(master); in tegra_spi_transfer_one_message() local
1052 reinit_completion(&tspi->xfer_completion); in tegra_spi_transfer_one_message()
1065 dev_err(tspi->dev, in tegra_spi_transfer_one_message()
1071 ret = wait_for_completion_timeout(&tspi->xfer_completion, in tegra_spi_transfer_one_message()
1074 dev_err(tspi->dev, in tegra_spi_transfer_one_message()
1076 if (tspi->is_curr_dma_xfer && in tegra_spi_transfer_one_message()
1077 (tspi->cur_direction & DATA_DIR_TX)) in tegra_spi_transfer_one_message()
1078 dmaengine_terminate_all(tspi->tx_dma_chan); in tegra_spi_transfer_one_message()
1079 if (tspi->is_curr_dma_xfer && in tegra_spi_transfer_one_message()
1080 (tspi->cur_direction & DATA_DIR_RX)) in tegra_spi_transfer_one_message()
1081 dmaengine_terminate_all(tspi->rx_dma_chan); in tegra_spi_transfer_one_message()
1083 tegra_spi_dump_regs(tspi); in tegra_spi_transfer_one_message()
1084 tegra_spi_flush_fifos(tspi); in tegra_spi_transfer_one_message()
1085 reset_control_assert(tspi->rst); in tegra_spi_transfer_one_message()
1087 reset_control_deassert(tspi->rst); in tegra_spi_transfer_one_message()
1088 tspi->last_used_cs = master->num_chipselect + 1; in tegra_spi_transfer_one_message()
1092 if (tspi->tx_status || tspi->rx_status) { in tegra_spi_transfer_one_message()
1093 dev_err(tspi->dev, "Error in Transfer\n"); in tegra_spi_transfer_one_message()
1095 tegra_spi_dump_regs(tspi); in tegra_spi_transfer_one_message()
1108 tspi->cs_control = spi; in tegra_spi_transfer_one_message()
1126 static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi) in handle_cpu_based_xfer() argument
1128 struct spi_transfer *t = tspi->curr_xfer; in handle_cpu_based_xfer()
1131 spin_lock_irqsave(&tspi->lock, flags); in handle_cpu_based_xfer()
1132 if (tspi->tx_status || tspi->rx_status) { in handle_cpu_based_xfer()
1133 dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n", in handle_cpu_based_xfer()
1134 tspi->status_reg); in handle_cpu_based_xfer()
1135 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n", in handle_cpu_based_xfer()
1136 tspi->command1_reg, tspi->dma_control_reg); in handle_cpu_based_xfer()
1137 tegra_spi_dump_regs(tspi); in handle_cpu_based_xfer()
1138 tegra_spi_flush_fifos(tspi); in handle_cpu_based_xfer()
1139 complete(&tspi->xfer_completion); in handle_cpu_based_xfer()
1140 spin_unlock_irqrestore(&tspi->lock, flags); in handle_cpu_based_xfer()
1141 reset_control_assert(tspi->rst); in handle_cpu_based_xfer()
1143 reset_control_deassert(tspi->rst); in handle_cpu_based_xfer()
1147 if (tspi->cur_direction & DATA_DIR_RX) in handle_cpu_based_xfer()
1148 tegra_spi_read_rx_fifo_to_client_rxbuf(tspi, t); in handle_cpu_based_xfer()
1150 if (tspi->cur_direction & DATA_DIR_TX) in handle_cpu_based_xfer()
1151 tspi->cur_pos = tspi->cur_tx_pos; in handle_cpu_based_xfer()
1153 tspi->cur_pos = tspi->cur_rx_pos; in handle_cpu_based_xfer()
1155 if (tspi->cur_pos == t->len) { in handle_cpu_based_xfer()
1156 complete(&tspi->xfer_completion); in handle_cpu_based_xfer()
1160 tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, t); in handle_cpu_based_xfer()
1161 tegra_spi_start_cpu_based_transfer(tspi, t); in handle_cpu_based_xfer()
1163 spin_unlock_irqrestore(&tspi->lock, flags); in handle_cpu_based_xfer()
1167 static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi) in handle_dma_based_xfer() argument
1169 struct spi_transfer *t = tspi->curr_xfer; in handle_dma_based_xfer()
1176 if (tspi->cur_direction & DATA_DIR_TX) { in handle_dma_based_xfer()
1177 if (tspi->tx_status) { in handle_dma_based_xfer()
1178 dmaengine_terminate_all(tspi->tx_dma_chan); in handle_dma_based_xfer()
1182 &tspi->tx_dma_complete, SPI_DMA_TIMEOUT); in handle_dma_based_xfer()
1184 dmaengine_terminate_all(tspi->tx_dma_chan); in handle_dma_based_xfer()
1185 dev_err(tspi->dev, "TxDma Xfer failed\n"); in handle_dma_based_xfer()
1191 if (tspi->cur_direction & DATA_DIR_RX) { in handle_dma_based_xfer()
1192 if (tspi->rx_status) { in handle_dma_based_xfer()
1193 dmaengine_terminate_all(tspi->rx_dma_chan); in handle_dma_based_xfer()
1197 &tspi->rx_dma_complete, SPI_DMA_TIMEOUT); in handle_dma_based_xfer()
1199 dmaengine_terminate_all(tspi->rx_dma_chan); in handle_dma_based_xfer()
1200 dev_err(tspi->dev, "RxDma Xfer failed\n"); in handle_dma_based_xfer()
1206 spin_lock_irqsave(&tspi->lock, flags); in handle_dma_based_xfer()
1208 dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n", in handle_dma_based_xfer()
1209 tspi->status_reg); in handle_dma_based_xfer()
1210 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n", in handle_dma_based_xfer()
1211 tspi->command1_reg, tspi->dma_control_reg); in handle_dma_based_xfer()
1212 tegra_spi_dump_regs(tspi); in handle_dma_based_xfer()
1213 tegra_spi_flush_fifos(tspi); in handle_dma_based_xfer()
1214 complete(&tspi->xfer_completion); in handle_dma_based_xfer()
1215 spin_unlock_irqrestore(&tspi->lock, flags); in handle_dma_based_xfer()
1216 reset_control_assert(tspi->rst); in handle_dma_based_xfer()
1218 reset_control_deassert(tspi->rst); in handle_dma_based_xfer()
1222 if (tspi->cur_direction & DATA_DIR_RX) in handle_dma_based_xfer()
1223 tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi, t); in handle_dma_based_xfer()
1225 if (tspi->cur_direction & DATA_DIR_TX) in handle_dma_based_xfer()
1226 tspi->cur_pos = tspi->cur_tx_pos; in handle_dma_based_xfer()
1228 tspi->cur_pos = tspi->cur_rx_pos; in handle_dma_based_xfer()
1230 if (tspi->cur_pos == t->len) { in handle_dma_based_xfer()
1231 complete(&tspi->xfer_completion); in handle_dma_based_xfer()
1236 total_fifo_words = tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, in handle_dma_based_xfer()
1237 tspi, t); in handle_dma_based_xfer()
1239 err = tegra_spi_start_dma_based_transfer(tspi, t); in handle_dma_based_xfer()
1241 err = tegra_spi_start_cpu_based_transfer(tspi, t); in handle_dma_based_xfer()
1244 spin_unlock_irqrestore(&tspi->lock, flags); in handle_dma_based_xfer()
1250 struct tegra_spi_data *tspi = context_data; in tegra_spi_isr_thread() local
1252 if (!tspi->is_curr_dma_xfer) in tegra_spi_isr_thread()
1253 return handle_cpu_based_xfer(tspi); in tegra_spi_isr_thread()
1254 return handle_dma_based_xfer(tspi); in tegra_spi_isr_thread()
1259 struct tegra_spi_data *tspi = context_data; in tegra_spi_isr() local
1261 tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS); in tegra_spi_isr()
1262 if (tspi->cur_direction & DATA_DIR_TX) in tegra_spi_isr()
1263 tspi->tx_status = tspi->status_reg & in tegra_spi_isr()
1266 if (tspi->cur_direction & DATA_DIR_RX) in tegra_spi_isr()
1267 tspi->rx_status = tspi->status_reg & in tegra_spi_isr()
1269 tegra_spi_clear_status(tspi); in tegra_spi_isr()
1304 struct tegra_spi_data *tspi; in tegra_spi_probe() local
1309 master = spi_alloc_master(&pdev->dev, sizeof(*tspi)); in tegra_spi_probe()
1315 tspi = spi_master_get_devdata(master); in tegra_spi_probe()
1336 tspi->master = master; in tegra_spi_probe()
1337 tspi->dev = &pdev->dev; in tegra_spi_probe()
1338 spin_lock_init(&tspi->lock); in tegra_spi_probe()
1340 tspi->soc_data = of_device_get_match_data(&pdev->dev); in tegra_spi_probe()
1341 if (!tspi->soc_data) { in tegra_spi_probe()
1348 tspi->base = devm_ioremap_resource(&pdev->dev, r); in tegra_spi_probe()
1349 if (IS_ERR(tspi->base)) { in tegra_spi_probe()
1350 ret = PTR_ERR(tspi->base); in tegra_spi_probe()
1353 tspi->phys = r->start; in tegra_spi_probe()
1360 tspi->irq = spi_irq; in tegra_spi_probe()
1362 tspi->clk = devm_clk_get(&pdev->dev, "spi"); in tegra_spi_probe()
1363 if (IS_ERR(tspi->clk)) { in tegra_spi_probe()
1365 ret = PTR_ERR(tspi->clk); in tegra_spi_probe()
1369 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi"); in tegra_spi_probe()
1370 if (IS_ERR(tspi->rst)) { in tegra_spi_probe()
1372 ret = PTR_ERR(tspi->rst); in tegra_spi_probe()
1376 tspi->max_buf_size = SPI_FIFO_DEPTH << 2; in tegra_spi_probe()
1377 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; in tegra_spi_probe()
1379 ret = tegra_spi_init_dma_param(tspi, true); in tegra_spi_probe()
1382 ret = tegra_spi_init_dma_param(tspi, false); in tegra_spi_probe()
1385 tspi->max_buf_size = tspi->dma_buf_size; in tegra_spi_probe()
1386 init_completion(&tspi->tx_dma_complete); in tegra_spi_probe()
1387 init_completion(&tspi->rx_dma_complete); in tegra_spi_probe()
1389 init_completion(&tspi->xfer_completion); in tegra_spi_probe()
1405 reset_control_assert(tspi->rst); in tegra_spi_probe()
1407 reset_control_deassert(tspi->rst); in tegra_spi_probe()
1408 tspi->def_command1_reg = SPI_M_S; in tegra_spi_probe()
1409 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); in tegra_spi_probe()
1410 tspi->spi_cs_timing1 = tegra_spi_readl(tspi, SPI_CS_TIMING1); in tegra_spi_probe()
1411 tspi->spi_cs_timing2 = tegra_spi_readl(tspi, SPI_CS_TIMING2); in tegra_spi_probe()
1412 tspi->def_command2_reg = tegra_spi_readl(tspi, SPI_COMMAND2); in tegra_spi_probe()
1413 tspi->last_used_cs = master->num_chipselect + 1; in tegra_spi_probe()
1415 ret = request_threaded_irq(tspi->irq, tegra_spi_isr, in tegra_spi_probe()
1417 dev_name(&pdev->dev), tspi); in tegra_spi_probe()
1420 tspi->irq); in tegra_spi_probe()
1433 free_irq(spi_irq, tspi); in tegra_spi_probe()
1438 tegra_spi_deinit_dma_param(tspi, false); in tegra_spi_probe()
1440 tegra_spi_deinit_dma_param(tspi, true); in tegra_spi_probe()
1449 struct tegra_spi_data *tspi = spi_master_get_devdata(master); in tegra_spi_remove() local
1451 free_irq(tspi->irq, tspi); in tegra_spi_remove()
1453 if (tspi->tx_dma_chan) in tegra_spi_remove()
1454 tegra_spi_deinit_dma_param(tspi, false); in tegra_spi_remove()
1456 if (tspi->rx_dma_chan) in tegra_spi_remove()
1457 tegra_spi_deinit_dma_param(tspi, true); in tegra_spi_remove()
1477 struct tegra_spi_data *tspi = spi_master_get_devdata(master); in tegra_spi_resume() local
1486 tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1); in tegra_spi_resume()
1487 tegra_spi_writel(tspi, tspi->def_command2_reg, SPI_COMMAND2); in tegra_spi_resume()
1488 tspi->last_used_cs = master->num_chipselect + 1; in tegra_spi_resume()
1498 struct tegra_spi_data *tspi = spi_master_get_devdata(master); in tegra_spi_runtime_suspend() local
1501 tegra_spi_readl(tspi, SPI_COMMAND1); in tegra_spi_runtime_suspend()
1503 clk_disable_unprepare(tspi->clk); in tegra_spi_runtime_suspend()
1510 struct tegra_spi_data *tspi = spi_master_get_devdata(master); in tegra_spi_runtime_resume() local
1513 ret = clk_prepare_enable(tspi->clk); in tegra_spi_runtime_resume()
1515 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret); in tegra_spi_runtime_resume()