177 	u32 rxfifo_op;  member
212 	.rxfifo_op		= 0x130,
235 	.rxfifo_op		= 0x130,
496 	writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op);  in spi_sirfsoc_dma_transfer()
501 			sspi->base + sspi->regs->rxfifo_op);  in spi_sirfsoc_dma_transfer()
507 		writel(0x0, sspi->base + sspi->regs->rxfifo_op);  in spi_sirfsoc_dma_transfer()
512 		writel(0x0, sspi->base + sspi->regs->rxfifo_op);  in spi_sirfsoc_dma_transfer()
574 			sspi->base + sspi->regs->rxfifo_op);  in spi_sirfsoc_dma_transfer()
598 	writel(0, sspi->base + sspi->regs->rxfifo_op);  in spi_sirfsoc_dma_transfer()
617 			sspi->base + sspi->regs->rxfifo_op);  in spi_sirfsoc_pio_transfer()
622 			writel(0x0, sspi->base + sspi->regs->rxfifo_op);  in spi_sirfsoc_pio_transfer()
635 			writel(0x0, sspi->base + sspi->regs->rxfifo_op);  in spi_sirfsoc_pio_transfer()
649 				sspi->base + sspi->regs->rxfifo_op);  in spi_sirfsoc_pio_transfer()
680 				sspi->base + sspi->regs->rxfifo_op);  in spi_sirfsoc_pio_transfer()
699 		writel(0, sspi->base + sspi->regs->rxfifo_op);  in spi_sirfsoc_pio_transfer()
1212 	writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op);  in spi_sirfsoc_resume()
1214 	writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->rxfifo_op);  in spi_sirfsoc_resume()