99 static void sifive_spi_write(struct sifive_spi *spi, int offset, u32 value)  in sifive_spi_write()  function
112 	sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);  in sifive_spi_init()
115 	sifive_spi_write(spi, SIFIVE_SPI_REG_TXMARK, 1);  in sifive_spi_init()
116 	sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK, 0);  in sifive_spi_init()
119 	sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY0,  in sifive_spi_init()
122 	sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY1,  in sifive_spi_init()
127 	sifive_spi_write(spi, SIFIVE_SPI_REG_FCTRL, 0);  in sifive_spi_init()
141 	sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);  in sifive_spi_prepare_message()
144 	sifive_spi_write(spi, SIFIVE_SPI_REG_CSID, device->chip_select);  in sifive_spi_prepare_message()
147 	sifive_spi_write(spi, SIFIVE_SPI_REG_SCKMODE,  in sifive_spi_prepare_message()
161 	sifive_spi_write(spi, SIFIVE_SPI_REG_CSMODE, is_high ?  in sifive_spi_set_cs()
176 	sifive_spi_write(spi, SIFIVE_SPI_REG_SCKDIV, cr);  in sifive_spi_prep_transfer()
197 	sifive_spi_write(spi, SIFIVE_SPI_REG_FMT, cr);  in sifive_spi_prep_transfer()
215 		sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);  in sifive_spi_irq()
233 		sifive_spi_write(spi, SIFIVE_SPI_REG_IE, bit);  in sifive_spi_wait()
242 	sifive_spi_write(spi, SIFIVE_SPI_REG_TXDATA,  in sifive_spi_tx()
274 			sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK,  in sifive_spi_transfer_one()
354 	sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, 0xffffffffU);  in sifive_spi_probe()
356 	sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);  in sifive_spi_probe()
424 	sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);  in sifive_spi_remove()