Lines Matching refs:SPI_SH_CR1
26 #define SPI_SH_CR1 0x08 macro
133 while (spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) { in spi_sh_wait_receive_buffer()
145 while (!(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBE)) { in spi_sh_wait_write_buffer_empty()
163 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1); in spi_sh_send()
171 !(spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_TBF); in spi_sh_send()
201 spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1); in spi_sh_send()
202 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1); in spi_sh_send()
232 spi_sh_clear_bit(ss, SPI_SH_SSD | SPI_SH_SSDB, SPI_SH_CR1); in spi_sh_receive()
233 spi_sh_set_bit(ss, SPI_SH_SSA, SPI_SH_CR1); in spi_sh_receive()
246 spi_sh_read(ss, SPI_SH_CR1) & SPI_SH_RBE) { in spi_sh_receive()
316 spi_sh_set_bit(ss, SPI_SH_SSD, SPI_SH_CR1); in spi_sh_work()
320 SPI_SH_CR1); in spi_sh_work()
334 SPI_SH_CR1); in spi_sh_work()
345 spi_sh_write(ss, 0xfe, SPI_SH_CR1); /* SPI sycle stop */ in spi_sh_setup()
346 spi_sh_write(ss, 0x00, SPI_SH_CR1); /* CR1 init */ in spi_sh_setup()
371 spi_sh_clear_bit(ss, SPI_SH_SSA, SPI_SH_CR1); in spi_sh_transfer()
388 SPI_SH_CR1); in spi_sh_cleanup()
396 cr1 = spi_sh_read(ss, SPI_SH_CR1); in spi_sh_irq()