246 				     u32 *sccr1_reg)  in pxa2xx_spi_clear_rx_thre()  argument
261 	*sccr1_reg &= ~mask;  in pxa2xx_spi_clear_rx_thre()
265 				   u32 *sccr1_reg, u32 threshold)  in pxa2xx_spi_set_rx_thre()  argument
269 		*sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);  in pxa2xx_spi_set_rx_thre()
272 		*sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);  in pxa2xx_spi_set_rx_thre()
275 		*sccr1_reg |= SSCR1_RxTresh(threshold);  in pxa2xx_spi_set_rx_thre()
603 	u32 sccr1_reg;  in reset_sccr1()  local
605 	sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;  in reset_sccr1()
608 		sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;  in reset_sccr1()
611 		sccr1_reg &= ~CE4100_SSCR1_RFT;  in reset_sccr1()
614 		sccr1_reg &= ~SSCR1_RFT;  in reset_sccr1()
617 	sccr1_reg |= chip->threshold;  in reset_sccr1()
618 	pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);  in reset_sccr1()
688 		u32 sccr1_reg;  in interrupt_transfer()  local
690 		sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);  in interrupt_transfer()
691 		sccr1_reg &= ~SSCR1_TIE;  in interrupt_transfer()
700 			pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);  in interrupt_transfer()
716 			pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);  in interrupt_transfer()
718 		pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);  in interrupt_transfer()
741 	u32 sccr1_reg;  in ssp_int()  local
764 	sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);  in ssp_int()
767 	if (!(sccr1_reg & SSCR1_TIE))  in ssp_int()
771 	if (!(sccr1_reg & SSCR1_TINTE))  in ssp_int()
777 	pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);  in ssp_int()
778 	pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);  in ssp_int()