221 	struct npcm_fiu_spi *fiu;  member
245 static void npcm_fiu_set_drd(struct npcm_fiu_spi *fiu,  in npcm_fiu_set_drd()  argument
248 	regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,  in npcm_fiu_set_drd()
252 	fiu->drd_op.addr.buswidth = op->addr.buswidth;  in npcm_fiu_set_drd()
253 	regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,  in npcm_fiu_set_drd()
257 	fiu->drd_op.dummy.nbytes = op->dummy.nbytes;  in npcm_fiu_set_drd()
258 	regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,  in npcm_fiu_set_drd()
260 	fiu->drd_op.cmd.opcode = op->cmd.opcode;  in npcm_fiu_set_drd()
261 	regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,  in npcm_fiu_set_drd()
264 	fiu->drd_op.addr.nbytes = op->addr.nbytes;  in npcm_fiu_set_drd()
270 	struct npcm_fiu_spi *fiu =  in npcm_fiu_direct_read()  local
272 	struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select];  in npcm_fiu_direct_read()
278 	if (fiu->spix_mode) {  in npcm_fiu_direct_read()
282 		if (desc->info.op_tmpl.addr.buswidth != fiu->drd_op.addr.buswidth ||  in npcm_fiu_direct_read()
283 		    desc->info.op_tmpl.dummy.nbytes != fiu->drd_op.dummy.nbytes ||  in npcm_fiu_direct_read()
284 		    desc->info.op_tmpl.cmd.opcode != fiu->drd_op.cmd.opcode ||  in npcm_fiu_direct_read()
285 		    desc->info.op_tmpl.addr.nbytes != fiu->drd_op.addr.nbytes)  in npcm_fiu_direct_read()
286 			npcm_fiu_set_drd(fiu, &desc->info.op_tmpl);  in npcm_fiu_direct_read()
297 	struct npcm_fiu_spi *fiu =  in npcm_fiu_direct_write()  local
299 	struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select];  in npcm_fiu_direct_write()
305 	if (fiu->spix_mode)  in npcm_fiu_direct_write()
318 	struct npcm_fiu_spi *fiu =  in npcm_fiu_uma_read()  local
326 	regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,  in npcm_fiu_uma_read()
330 	regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD,  in npcm_fiu_uma_read()
343 		regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, addr);  in npcm_fiu_uma_read()
345 		regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0);  in npcm_fiu_uma_read()
349 	regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg);  in npcm_fiu_uma_read()
350 	regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS,  in npcm_fiu_uma_read()
353 	ret = regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val,  in npcm_fiu_uma_read()
361 			regmap_read(fiu->regmap, NPCM_FIU_UMA_DR0 + (i * 4),  in npcm_fiu_uma_read()
373 	struct npcm_fiu_spi *fiu =  in npcm_fiu_uma_write()  local
380 	regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,  in npcm_fiu_uma_write()
385 	regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD,  in npcm_fiu_uma_write()
391 			regmap_write(fiu->regmap, NPCM_FIU_UMA_DW0 + (i * 4),  in npcm_fiu_uma_write()
402 		regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, op->addr.val);  in npcm_fiu_uma_write()
404 		regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0);  in npcm_fiu_uma_write()
408 	regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg);  in npcm_fiu_uma_write()
410 	regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS,  in npcm_fiu_uma_write()
414 	return regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val,  in npcm_fiu_uma_write()
422 	struct npcm_fiu_spi *fiu =  in npcm_fiu_manualwrite()  local
433 	regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,  in npcm_fiu_manualwrite()
437 	regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,  in npcm_fiu_manualwrite()
462 	regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,  in npcm_fiu_manualwrite()
499 static void npcm_fiux_set_direct_wr(struct npcm_fiu_spi *fiu)  in npcm_fiux_set_direct_wr()  argument
501 	regmap_write(fiu->regmap, NPCM_FIU_DWR_CFG,  in npcm_fiux_set_direct_wr()
503 	regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG,  in npcm_fiux_set_direct_wr()
506 	regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG,  in npcm_fiux_set_direct_wr()
511 static void npcm_fiux_set_direct_rd(struct npcm_fiu_spi *fiu)  in npcm_fiux_set_direct_rd()  argument
515 	regmap_write(fiu->regmap, NPCM_FIU_DRD_CFG,  in npcm_fiux_set_direct_rd()
517 	regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,  in npcm_fiux_set_direct_rd()
520 	regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,  in npcm_fiux_set_direct_rd()
527 	struct npcm_fiu_spi *fiu =  in npcm_fiu_exec_op()  local
529 	struct npcm_fiu_chip *chip = &fiu->chip[mem->spi->chip_select];  in npcm_fiu_exec_op()
533 	dev_dbg(fiu->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",  in npcm_fiu_exec_op()
538 	if (fiu->spix_mode || op->addr.nbytes > 4)  in npcm_fiu_exec_op()
541 	if (fiu->clkrate != chip->clkrate) {  in npcm_fiu_exec_op()
542 		ret = clk_set_rate(fiu->clk, chip->clkrate);  in npcm_fiu_exec_op()
544 			dev_warn(fiu->dev, "Failed setting %lu frequency, stay at %lu frequency\n",  in npcm_fiu_exec_op()
545 				 chip->clkrate, fiu->clkrate);  in npcm_fiu_exec_op()
547 			fiu->clkrate = chip->clkrate;  in npcm_fiu_exec_op()
587 	struct npcm_fiu_spi *fiu =  in npcm_fiu_dirmap_create()  local
589 	struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select];  in npcm_fiu_dirmap_create()
592 	if (!fiu->res_mem) {  in npcm_fiu_dirmap_create()
593 		dev_warn(fiu->dev, "Reserved memory not defined, direct read disabled\n");  in npcm_fiu_dirmap_create()
598 	if (!fiu->spix_mode &&  in npcm_fiu_dirmap_create()
606 			devm_ioremap(fiu->dev, (fiu->res_mem->start +  in npcm_fiu_dirmap_create()
607 							(fiu->info->max_map_size *  in npcm_fiu_dirmap_create()
611 			dev_warn(fiu->dev, "Error mapping memory region, direct read disabled\n");  in npcm_fiu_dirmap_create()
617 	if (of_device_is_compatible(fiu->dev->of_node, "nuvoton,npcm750-fiu")) {  in npcm_fiu_dirmap_create()
621 			dev_warn(fiu->dev, "Didn't find nuvoton,npcm750-gcr, direct read disabled\n");  in npcm_fiu_dirmap_create()
631 		if (!fiu->spix_mode)  in npcm_fiu_dirmap_create()
632 			npcm_fiu_set_drd(fiu, &desc->info.op_tmpl);  in npcm_fiu_dirmap_create()
634 			npcm_fiux_set_direct_rd(fiu);  in npcm_fiu_dirmap_create()
637 		npcm_fiux_set_direct_wr(fiu);  in npcm_fiu_dirmap_create()
646 	struct npcm_fiu_spi *fiu = spi_controller_get_devdata(ctrl);  in npcm_fiu_setup()  local
649 	chip = &fiu->chip[spi->chip_select];  in npcm_fiu_setup()
650 	chip->fiu = fiu;  in npcm_fiu_setup()
654 	fiu->clkrate = clk_get_rate(fiu->clk);  in npcm_fiu_setup()
677 	struct npcm_fiu_spi *fiu;  in npcm_fiu_probe()  local
682 	ctrl = devm_spi_alloc_master(dev, sizeof(*fiu));  in npcm_fiu_probe()
686 	fiu = spi_controller_get_devdata(ctrl);  in npcm_fiu_probe()
701 	fiu->info = &fiu_data_match->npcm_fiu_data_info[id];  in npcm_fiu_probe()
703 	platform_set_drvdata(pdev, fiu);  in npcm_fiu_probe()
704 	fiu->dev = dev;  in npcm_fiu_probe()
711 	fiu->regmap = devm_regmap_init_mmio(dev, regbase,  in npcm_fiu_probe()
713 	if (IS_ERR(fiu->regmap)) {  in npcm_fiu_probe()
715 		return PTR_ERR(fiu->regmap);  in npcm_fiu_probe()
718 	fiu->res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM,  in npcm_fiu_probe()
720 	fiu->clk = devm_clk_get(dev, NULL);  in npcm_fiu_probe()
721 	if (IS_ERR(fiu->clk))  in npcm_fiu_probe()
722 		return PTR_ERR(fiu->clk);  in npcm_fiu_probe()
724 	fiu->spix_mode = of_property_read_bool(dev->of_node,  in npcm_fiu_probe()
727 	platform_set_drvdata(pdev, fiu);  in npcm_fiu_probe()
728 	clk_prepare_enable(fiu->clk);  in npcm_fiu_probe()
735 	ctrl->num_chipselect = fiu->info->max_cs;  in npcm_fiu_probe()
740 		clk_disable_unprepare(fiu->clk);  in npcm_fiu_probe()
747 	struct npcm_fiu_spi *fiu = platform_get_drvdata(pdev);  in npcm_fiu_remove()  local
749 	clk_disable_unprepare(fiu->clk);  in npcm_fiu_remove()