Lines Matching +full:mt8173 +full:- +full:nor
1 // SPDX-License-Identifier: GPL-2.0
3 // Mediatek SPI NOR controller driver
10 #include <linux/dma-mapping.h>
19 #include <linux/spi/spi-mem.h>
22 #define DRIVER_NAME "mtk-spi-nor"
87 // Reading DMA src/dst addresses have to be 16-byte aligned
89 #define MTK_NOR_DMA_ALIGN_MASK (MTK_NOR_DMA_ALIGN - 1)
93 // Buffered page program can do one 128-byte transfer
96 #define CLK_TO_US(sp, clkcnt) DIV_ROUND_UP(clkcnt, sp->spi_freq / 1000000)
115 u32 val = readl(sp->base + reg); in mtk_nor_rmw()
119 writel(val, sp->base + reg); in mtk_nor_rmw()
128 writel(cmd, sp->base + MTK_NOR_REG_CMD); in mtk_nor_cmd_exec()
129 ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CMD, reg, !(reg & cmd), in mtk_nor_cmd_exec()
132 dev_err(sp->dev, "command %u timeout.\n", cmd); in mtk_nor_cmd_exec()
138 u32 addr = op->addr.val; in mtk_nor_set_addr()
142 writeb(addr & 0xff, sp->base + MTK_NOR_REG_RADR(i)); in mtk_nor_set_addr()
145 if (op->addr.nbytes == 4) { in mtk_nor_set_addr()
146 writeb(addr & 0xff, sp->base + MTK_NOR_REG_RADR3); in mtk_nor_set_addr()
155 return ((uintptr_t)op->data.buf.in & MTK_NOR_DMA_ALIGN_MASK); in need_bounce()
162 if (op->dummy.buswidth) in mtk_nor_match_read()
163 dummy = op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth; in mtk_nor_match_read()
165 if ((op->data.buswidth == 2) || (op->data.buswidth == 4)) { in mtk_nor_match_read()
166 if (op->addr.buswidth == 1) in mtk_nor_match_read()
168 else if (op->addr.buswidth == 2) in mtk_nor_match_read()
170 else if (op->addr.buswidth == 4) in mtk_nor_match_read()
172 } else if ((op->addr.buswidth == 1) && (op->data.buswidth == 1)) { in mtk_nor_match_read()
173 if (op->cmd.opcode == 0x03) in mtk_nor_match_read()
175 else if (op->cmd.opcode == 0x0b) in mtk_nor_match_read()
185 // prg mode is spi-only. in mtk_nor_match_prg()
186 if ((op->cmd.buswidth > 1) || (op->addr.buswidth > 1) || in mtk_nor_match_prg()
187 (op->dummy.buswidth > 1) || (op->data.buswidth > 1)) in mtk_nor_match_prg()
190 tx_len = op->cmd.nbytes + op->addr.nbytes; in mtk_nor_match_prg()
192 if (op->data.dir == SPI_MEM_DATA_OUT) { in mtk_nor_match_prg()
194 tx_len += op->dummy.nbytes; in mtk_nor_match_prg()
202 if ((!op->addr.nbytes) && in mtk_nor_match_prg()
203 (tx_len + op->data.nbytes > MTK_NOR_REG_PRGDATA_MAX + 1)) in mtk_nor_match_prg()
205 } else if (op->data.dir == SPI_MEM_DATA_IN) { in mtk_nor_match_prg()
209 rx_len = op->data.nbytes; in mtk_nor_match_prg()
210 prg_left = MTK_NOR_PRG_CNT_MAX / 8 - tx_len - op->dummy.nbytes; in mtk_nor_match_prg()
214 if (!op->addr.nbytes) in mtk_nor_match_prg()
219 prg_len = tx_len + op->dummy.nbytes + rx_len; in mtk_nor_match_prg()
223 prg_len = tx_len + op->dummy.nbytes; in mtk_nor_match_prg()
234 tx_len = op->cmd.nbytes + op->addr.nbytes; in mtk_nor_adj_prg_size()
235 if (op->data.dir == SPI_MEM_DATA_OUT) { in mtk_nor_adj_prg_size()
236 tx_len += op->dummy.nbytes; in mtk_nor_adj_prg_size()
237 tx_left = MTK_NOR_REG_PRGDATA_MAX + 1 - tx_len; in mtk_nor_adj_prg_size()
238 if (op->data.nbytes > tx_left) in mtk_nor_adj_prg_size()
239 op->data.nbytes = tx_left; in mtk_nor_adj_prg_size()
240 } else if (op->data.dir == SPI_MEM_DATA_IN) { in mtk_nor_adj_prg_size()
241 prg_left = MTK_NOR_PRG_CNT_MAX / 8 - tx_len - op->dummy.nbytes; in mtk_nor_adj_prg_size()
244 if (op->data.nbytes > prg_left) in mtk_nor_adj_prg_size()
245 op->data.nbytes = prg_left; in mtk_nor_adj_prg_size()
251 struct mtk_nor *sp = spi_controller_get_devdata(mem->spi->master); in mtk_nor_adjust_op_size()
253 if (!op->data.nbytes) in mtk_nor_adjust_op_size()
256 if ((op->addr.nbytes == 3) || (op->addr.nbytes == 4)) { in mtk_nor_adjust_op_size()
257 if ((op->data.dir == SPI_MEM_DATA_IN) && in mtk_nor_adjust_op_size()
260 if (op->data.nbytes > 0x400000) in mtk_nor_adjust_op_size()
261 op->data.nbytes = 0x400000; in mtk_nor_adjust_op_size()
263 if ((op->addr.val & MTK_NOR_DMA_ALIGN_MASK) || in mtk_nor_adjust_op_size()
264 (op->data.nbytes < MTK_NOR_DMA_ALIGN)) in mtk_nor_adjust_op_size()
265 op->data.nbytes = 1; in mtk_nor_adjust_op_size()
267 op->data.nbytes &= ~MTK_NOR_DMA_ALIGN_MASK; in mtk_nor_adjust_op_size()
268 else if (op->data.nbytes > MTK_NOR_BOUNCE_BUF_SIZE) in mtk_nor_adjust_op_size()
269 op->data.nbytes = MTK_NOR_BOUNCE_BUF_SIZE; in mtk_nor_adjust_op_size()
271 } else if (op->data.dir == SPI_MEM_DATA_OUT) { in mtk_nor_adjust_op_size()
272 if (op->data.nbytes >= MTK_NOR_PP_SIZE) in mtk_nor_adjust_op_size()
273 op->data.nbytes = MTK_NOR_PP_SIZE; in mtk_nor_adjust_op_size()
275 op->data.nbytes = 1; in mtk_nor_adjust_op_size()
290 if (op->cmd.buswidth != 1) in mtk_nor_supports_op()
293 if ((op->addr.nbytes == 3) || (op->addr.nbytes == 4)) { in mtk_nor_supports_op()
294 switch(op->data.dir) { in mtk_nor_supports_op()
300 if ((op->addr.buswidth == 1) && in mtk_nor_supports_op()
301 (op->dummy.nbytes == 0) && in mtk_nor_supports_op()
302 (op->data.buswidth == 1)) in mtk_nor_supports_op()
317 if (op->addr.nbytes == 4) in mtk_nor_setup_bus()
320 if (op->data.buswidth == 4) { in mtk_nor_setup_bus()
322 writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA(4)); in mtk_nor_setup_bus()
323 if (op->addr.buswidth == 4) in mtk_nor_setup_bus()
325 } else if (op->data.buswidth == 2) { in mtk_nor_setup_bus()
327 writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA(3)); in mtk_nor_setup_bus()
328 if (op->addr.buswidth == 2) in mtk_nor_setup_bus()
331 if (op->cmd.opcode == 0x0b) in mtk_nor_setup_bus()
346 writel(from, sp->base + MTK_NOR_REG_DMA_FADR); in mtk_nor_dma_exec()
347 writel(dma_addr, sp->base + MTK_NOR_REG_DMA_DADR); in mtk_nor_dma_exec()
348 writel(dma_addr + length, sp->base + MTK_NOR_REG_DMA_END_DADR); in mtk_nor_dma_exec()
350 if (sp->high_dma) { in mtk_nor_dma_exec()
352 sp->base + MTK_NOR_REG_DMA_DADR_HB); in mtk_nor_dma_exec()
354 sp->base + MTK_NOR_REG_DMA_END_DADR_HB); in mtk_nor_dma_exec()
357 if (sp->has_irq) { in mtk_nor_dma_exec()
358 reinit_completion(&sp->op_done); in mtk_nor_dma_exec()
366 if (sp->has_irq) { in mtk_nor_dma_exec()
367 if (!wait_for_completion_timeout(&sp->op_done, in mtk_nor_dma_exec()
369 ret = -ETIMEDOUT; in mtk_nor_dma_exec()
371 ret = readl_poll_timeout(sp->base + MTK_NOR_REG_DMA_CTL, reg, in mtk_nor_dma_exec()
377 dev_err(sp->dev, "dma read timeout.\n"); in mtk_nor_dma_exec()
387 if (op->data.nbytes & MTK_NOR_DMA_ALIGN_MASK) in mtk_nor_read_bounce()
388 rdlen = (op->data.nbytes + MTK_NOR_DMA_ALIGN) & ~MTK_NOR_DMA_ALIGN_MASK; in mtk_nor_read_bounce()
390 rdlen = op->data.nbytes; in mtk_nor_read_bounce()
392 ret = mtk_nor_dma_exec(sp, op->addr.val, rdlen, sp->buffer_dma); in mtk_nor_read_bounce()
395 memcpy(op->data.buf.in, sp->buffer, op->data.nbytes); in mtk_nor_read_bounce()
408 dma_addr = dma_map_single(sp->dev, op->data.buf.in, in mtk_nor_read_dma()
409 op->data.nbytes, DMA_FROM_DEVICE); in mtk_nor_read_dma()
411 if (dma_mapping_error(sp->dev, dma_addr)) in mtk_nor_read_dma()
412 return -EINVAL; in mtk_nor_read_dma()
414 ret = mtk_nor_dma_exec(sp, op->addr.val, op->data.nbytes, dma_addr); in mtk_nor_read_dma()
416 dma_unmap_single(sp->dev, dma_addr, op->data.nbytes, DMA_FROM_DEVICE); in mtk_nor_read_dma()
423 u8 *buf = op->data.buf.in; in mtk_nor_read_pio()
428 buf[0] = readb(sp->base + MTK_NOR_REG_RDATA); in mtk_nor_read_pio()
437 if (sp->wbuf_en) in mtk_nor_write_buffer_enable()
440 val = readl(sp->base + MTK_NOR_REG_CFG2); in mtk_nor_write_buffer_enable()
441 writel(val | MTK_NOR_WR_BUF_EN, sp->base + MTK_NOR_REG_CFG2); in mtk_nor_write_buffer_enable()
442 ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CFG2, val, in mtk_nor_write_buffer_enable()
445 sp->wbuf_en = true; in mtk_nor_write_buffer_enable()
454 if (!sp->wbuf_en) in mtk_nor_write_buffer_disable()
456 val = readl(sp->base + MTK_NOR_REG_CFG2); in mtk_nor_write_buffer_disable()
457 writel(val & ~MTK_NOR_WR_BUF_EN, sp->base + MTK_NOR_REG_CFG2); in mtk_nor_write_buffer_disable()
458 ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CFG2, val, in mtk_nor_write_buffer_disable()
461 sp->wbuf_en = false; in mtk_nor_write_buffer_disable()
467 const u8 *buf = op->data.buf.out; in mtk_nor_pp_buffered()
475 for (i = 0; i < op->data.nbytes; i += 4) { in mtk_nor_pp_buffered()
478 writel(val, sp->base + MTK_NOR_REG_PP_DATA); in mtk_nor_pp_buffered()
481 (op->data.nbytes + 5) * BITS_PER_BYTE); in mtk_nor_pp_buffered()
487 const u8 *buf = op->data.buf.out; in mtk_nor_pp_unbuffered()
493 writeb(buf[0], sp->base + MTK_NOR_REG_WDATA); in mtk_nor_pp_unbuffered()
506 tx_len = op->cmd.nbytes + op->addr.nbytes; in mtk_nor_spi_mem_prg()
509 if (op->data.dir == SPI_MEM_DATA_OUT) in mtk_nor_spi_mem_prg()
510 tx_len += op->dummy.nbytes + op->data.nbytes; in mtk_nor_spi_mem_prg()
511 else if (op->data.dir == SPI_MEM_DATA_IN) in mtk_nor_spi_mem_prg()
512 rx_len = op->data.nbytes; in mtk_nor_spi_mem_prg()
514 prg_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes + in mtk_nor_spi_mem_prg()
515 op->data.nbytes; in mtk_nor_spi_mem_prg()
518 // adjust_op_size. return -EINVAL instead of -ENOTSUPP so that in mtk_nor_spi_mem_prg()
519 // spi-mem won't try this op again with generic spi transfers. in mtk_nor_spi_mem_prg()
523 return -EINVAL; in mtk_nor_spi_mem_prg()
526 for (i = op->cmd.nbytes; i > 0; i--, reg_offset--) { in mtk_nor_spi_mem_prg()
527 reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset); in mtk_nor_spi_mem_prg()
528 bufbyte = (op->cmd.opcode >> ((i - 1) * BITS_PER_BYTE)) & 0xff; in mtk_nor_spi_mem_prg()
532 for (i = op->addr.nbytes; i > 0; i--, reg_offset--) { in mtk_nor_spi_mem_prg()
533 reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset); in mtk_nor_spi_mem_prg()
534 bufbyte = (op->addr.val >> ((i - 1) * BITS_PER_BYTE)) & 0xff; in mtk_nor_spi_mem_prg()
538 if (op->data.dir == SPI_MEM_DATA_OUT) { in mtk_nor_spi_mem_prg()
539 for (i = 0; i < op->dummy.nbytes; i++, reg_offset--) { in mtk_nor_spi_mem_prg()
540 reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset); in mtk_nor_spi_mem_prg()
544 for (i = 0; i < op->data.nbytes; i++, reg_offset--) { in mtk_nor_spi_mem_prg()
545 reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset); in mtk_nor_spi_mem_prg()
546 writeb(((const u8 *)(op->data.buf.out))[i], reg); in mtk_nor_spi_mem_prg()
550 for (; reg_offset >= 0; reg_offset--) { in mtk_nor_spi_mem_prg()
551 reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset); in mtk_nor_spi_mem_prg()
556 writel(prg_len * BITS_PER_BYTE, sp->base + MTK_NOR_REG_PRG_CNT); in mtk_nor_spi_mem_prg()
564 if (op->data.dir == SPI_MEM_DATA_IN) { in mtk_nor_spi_mem_prg()
565 for (i = op->data.nbytes - 1; i >= 0; i--, reg_offset++) { in mtk_nor_spi_mem_prg()
566 reg = sp->base + MTK_NOR_REG_SHIFT(reg_offset); in mtk_nor_spi_mem_prg()
567 ((u8 *)(op->data.buf.in))[i] = readb(reg); in mtk_nor_spi_mem_prg()
576 struct mtk_nor *sp = spi_controller_get_devdata(mem->spi->master); in mtk_nor_exec_op()
579 if ((op->data.nbytes == 0) || in mtk_nor_exec_op()
580 ((op->addr.nbytes != 3) && (op->addr.nbytes != 4))) in mtk_nor_exec_op()
583 if (op->data.dir == SPI_MEM_DATA_OUT) { in mtk_nor_exec_op()
585 writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA0); in mtk_nor_exec_op()
586 if (op->data.nbytes == MTK_NOR_PP_SIZE) in mtk_nor_exec_op()
591 if ((op->data.dir == SPI_MEM_DATA_IN) && mtk_nor_match_read(op)) { in mtk_nor_exec_op()
596 if (op->data.nbytes == 1) { in mtk_nor_exec_op()
609 struct mtk_nor *sp = spi_controller_get_devdata(spi->master); in mtk_nor_setup()
611 if (spi->max_speed_hz && (spi->max_speed_hz < sp->spi_freq)) { in mtk_nor_setup()
612 dev_err(&spi->dev, "spi clock should be %u Hz.\n", in mtk_nor_setup()
613 sp->spi_freq); in mtk_nor_setup()
614 return -EINVAL; in mtk_nor_setup()
616 spi->max_speed_hz = sp->spi_freq; in mtk_nor_setup()
634 list_for_each_entry(t, &m->transfers, transfer_list) { in mtk_nor_transfer_one_message()
635 txbuf = t->tx_buf; in mtk_nor_transfer_one_message()
636 for (i = 0; i < t->len; i++, reg_offset--) { in mtk_nor_transfer_one_message()
637 reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset); in mtk_nor_transfer_one_message()
643 trx_len += t->len; in mtk_nor_transfer_one_message()
646 writel(trx_len * BITS_PER_BYTE, sp->base + MTK_NOR_REG_PRG_CNT); in mtk_nor_transfer_one_message()
653 reg_offset = trx_len - 1; in mtk_nor_transfer_one_message()
654 list_for_each_entry(t, &m->transfers, transfer_list) { in mtk_nor_transfer_one_message()
655 rxbuf = t->rx_buf; in mtk_nor_transfer_one_message()
656 for (i = 0; i < t->len; i++, reg_offset--) { in mtk_nor_transfer_one_message()
657 reg = sp->base + MTK_NOR_REG_SHIFT(reg_offset); in mtk_nor_transfer_one_message()
663 m->actual_length = trx_len; in mtk_nor_transfer_one_message()
665 m->status = stat; in mtk_nor_transfer_one_message()
673 clk_disable_unprepare(sp->spi_clk); in mtk_nor_disable_clk()
674 clk_disable_unprepare(sp->ctlr_clk); in mtk_nor_disable_clk()
681 ret = clk_prepare_enable(sp->spi_clk); in mtk_nor_enable_clk()
685 ret = clk_prepare_enable(sp->ctlr_clk); in mtk_nor_enable_clk()
687 clk_disable_unprepare(sp->spi_clk); in mtk_nor_enable_clk()
696 writel(0, sp->base + MTK_NOR_REG_IRQ_EN); in mtk_nor_init()
697 writel(MTK_NOR_IRQ_MASK, sp->base + MTK_NOR_REG_IRQ_STAT); in mtk_nor_init()
699 writel(MTK_NOR_ENABLE_SF_CMD, sp->base + MTK_NOR_REG_WP); in mtk_nor_init()
710 irq_status = readl(sp->base + MTK_NOR_REG_IRQ_STAT); in mtk_nor_irq_handler()
711 irq_enabled = readl(sp->base + MTK_NOR_REG_IRQ_EN); in mtk_nor_irq_handler()
713 writel(irq_status, sp->base + MTK_NOR_REG_IRQ_STAT); in mtk_nor_irq_handler()
719 complete(&sp->op_done); in mtk_nor_irq_handler()
720 writel(0, sp->base + MTK_NOR_REG_IRQ_EN); in mtk_nor_irq_handler()
738 { .compatible = "mediatek,mt8192-nor", .data = (void *)36 },
739 { .compatible = "mediatek,mt8173-nor", .data = (void *)32 },
757 spi_clk = devm_clk_get(&pdev->dev, "spi"); in mtk_nor_probe()
761 ctlr_clk = devm_clk_get(&pdev->dev, "sf"); in mtk_nor_probe()
765 dma_bits = (unsigned long)of_device_get_match_data(&pdev->dev); in mtk_nor_probe()
766 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits))) { in mtk_nor_probe()
767 dev_err(&pdev->dev, "failed to set dma mask(%lu)\n", dma_bits); in mtk_nor_probe()
768 return -EINVAL; in mtk_nor_probe()
771 ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*sp)); in mtk_nor_probe()
773 dev_err(&pdev->dev, "failed to allocate spi controller\n"); in mtk_nor_probe()
774 return -ENOMEM; in mtk_nor_probe()
777 ctlr->bits_per_word_mask = SPI_BPW_MASK(8); in mtk_nor_probe()
778 ctlr->dev.of_node = pdev->dev.of_node; in mtk_nor_probe()
779 ctlr->max_message_size = mtk_max_msg_size; in mtk_nor_probe()
780 ctlr->mem_ops = &mtk_nor_mem_ops; in mtk_nor_probe()
781 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; in mtk_nor_probe()
782 ctlr->num_chipselect = 1; in mtk_nor_probe()
783 ctlr->setup = mtk_nor_setup; in mtk_nor_probe()
784 ctlr->transfer_one_message = mtk_nor_transfer_one_message; in mtk_nor_probe()
785 ctlr->auto_runtime_pm = true; in mtk_nor_probe()
787 dev_set_drvdata(&pdev->dev, ctlr); in mtk_nor_probe()
790 sp->base = base; in mtk_nor_probe()
791 sp->has_irq = false; in mtk_nor_probe()
792 sp->wbuf_en = false; in mtk_nor_probe()
793 sp->ctlr = ctlr; in mtk_nor_probe()
794 sp->dev = &pdev->dev; in mtk_nor_probe()
795 sp->spi_clk = spi_clk; in mtk_nor_probe()
796 sp->ctlr_clk = ctlr_clk; in mtk_nor_probe()
797 sp->high_dma = (dma_bits > 32); in mtk_nor_probe()
798 sp->buffer = dmam_alloc_coherent(&pdev->dev, in mtk_nor_probe()
800 &sp->buffer_dma, GFP_KERNEL); in mtk_nor_probe()
801 if (!sp->buffer) in mtk_nor_probe()
802 return -ENOMEM; in mtk_nor_probe()
804 if ((uintptr_t)sp->buffer & MTK_NOR_DMA_ALIGN_MASK) { in mtk_nor_probe()
805 dev_err(sp->dev, "misaligned allocation of internal buffer.\n"); in mtk_nor_probe()
806 return -ENOMEM; in mtk_nor_probe()
813 sp->spi_freq = clk_get_rate(sp->spi_clk); in mtk_nor_probe()
820 dev_warn(sp->dev, "IRQ not available."); in mtk_nor_probe()
822 ret = devm_request_irq(sp->dev, irq, mtk_nor_irq_handler, 0, in mtk_nor_probe()
823 pdev->name, sp); in mtk_nor_probe()
825 dev_warn(sp->dev, "failed to request IRQ."); in mtk_nor_probe()
827 init_completion(&sp->op_done); in mtk_nor_probe()
828 sp->has_irq = true; in mtk_nor_probe()
832 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); in mtk_nor_probe()
833 pm_runtime_use_autosuspend(&pdev->dev); in mtk_nor_probe()
834 pm_runtime_set_active(&pdev->dev); in mtk_nor_probe()
835 pm_runtime_enable(&pdev->dev); in mtk_nor_probe()
836 pm_runtime_get_noresume(&pdev->dev); in mtk_nor_probe()
838 ret = devm_spi_register_controller(&pdev->dev, ctlr); in mtk_nor_probe()
842 pm_runtime_mark_last_busy(&pdev->dev); in mtk_nor_probe()
843 pm_runtime_put_autosuspend(&pdev->dev); in mtk_nor_probe()
845 dev_info(&pdev->dev, "spi frequency: %d Hz\n", sp->spi_freq); in mtk_nor_probe()
850 pm_runtime_disable(&pdev->dev); in mtk_nor_probe()
851 pm_runtime_set_suspended(&pdev->dev); in mtk_nor_probe()
852 pm_runtime_dont_use_autosuspend(&pdev->dev); in mtk_nor_probe()
861 struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev); in mtk_nor_remove()
864 pm_runtime_disable(&pdev->dev); in mtk_nor_remove()
865 pm_runtime_set_suspended(&pdev->dev); in mtk_nor_remove()
866 pm_runtime_dont_use_autosuspend(&pdev->dev); in mtk_nor_remove()
929 MODULE_DESCRIPTION("Mediatek SPI NOR controller driver");