Lines Matching refs:SPICC_CONREG
45 #define SPICC_CONREG 0x08 macro
266 spicc->base + SPICC_CONREG); in meson_spicc_setup_burst()
294 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); in meson_spicc_irq()
312 readl_relaxed(spicc->base + SPICC_CONREG)); in meson_spicc_auto_io_delay()
348 conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG); in meson_spicc_setup_xfer()
357 writel_relaxed(conf, spicc->base + SPICC_CONREG); in meson_spicc_setup_xfer()
414 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); in meson_spicc_transfer_one()
427 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK; in meson_spicc_prepare_message()
467 writel_relaxed(conf, spicc->base + SPICC_CONREG); in meson_spicc_prepare_message()
480 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK; in meson_spicc_unprepare_transfer()
488 writel_relaxed(conf, spicc->base + SPICC_CONREG); in meson_spicc_unprepare_transfer()
628 spicc->pow2_div.reg = spicc->base + SPICC_CONREG; in meson_spicc_pow2_clk_init()
755 spicc->base + SPICC_CONREG); in meson_spicc_probe()
861 writel(0, spicc->base + SPICC_CONREG); in meson_spicc_remove()