193 static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val,  in lantiq_ssc_writel()  function
235 	lantiq_ssc_writel(spi, val, LTQ_SPI_RXFCON);  in rx_fifo_reset()
243 	lantiq_ssc_writel(spi, val, LTQ_SPI_TXFCON);  in tx_fifo_reset()
258 	lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);  in hw_enter_config_mode()
263 	lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);  in hw_enter_active_mode()
292 	lantiq_ssc_writel(spi, brt, LTQ_SPI_BRT);  in hw_setup_speed_hz()
352 	lantiq_ssc_writel(spi, 1 << LTQ_SPI_CLC_RMC_S, LTQ_SPI_CLC);  in lantiq_ssc_hw_init()
361 	lantiq_ssc_writel(spi, LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |  in lantiq_ssc_hw_init()
370 	lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETMS |  in lantiq_ssc_hw_init()
375 	lantiq_ssc_writel(spi, 0, LTQ_SPI_GPOCON);  in lantiq_ssc_hw_init()
376 	lantiq_ssc_writel(spi, 0xFF00, LTQ_SPI_FPGO);  in lantiq_ssc_hw_init()
383 	lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r |  in lantiq_ssc_hw_init()
460 	lantiq_ssc_writel(spi, con, LTQ_SPI_CON);  in hw_setup_transfer()
512 		lantiq_ssc_writel(spi, data, LTQ_SPI_TB);  in tx_fifo_write()
620 	lantiq_ssc_writel(spi, rxreq, LTQ_SPI_RXREQ);  in rx_request()
631 		lantiq_ssc_writel(spi, val, hwcfg->irncr);  in lantiq_ssc_xmit_interrupt()
676 		lantiq_ssc_writel(spi, val, hwcfg->irncr);  in lantiq_ssc_err_interrupt()
807 	lantiq_ssc_writel(spi, fgpo, LTQ_SPI_FPGO);  in lantiq_ssc_set_cs()
1030 	lantiq_ssc_writel(spi, 0, LTQ_SPI_IRNEN);  in lantiq_ssc_remove()
1031 	lantiq_ssc_writel(spi, 0, LTQ_SPI_CLC);  in lantiq_ssc_remove()