135 	*value = 0ULL;  in fsi_spi_read_reg()
217 	*out = 0ULL;  in fsi_spi_data_out()
241 	return fsi_spi_write_reg(ctx, SPI_FSI_STATUS, 0ULL);  in fsi_spi_reset()
261 	seq->data = 0ULL;  in fsi_spi_sequence_init()
275 	u64 cfg = 0ULL;  in fsi_spi_sequence_transfer()
327 		fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, 0ULL);  in fsi_spi_sequence_transfer()
340 	u64 status = 0ULL;  in fsi_spi_transfer_data()
341 	u64 cfg = 0ULL;  in fsi_spi_transfer_data()
346 		u64 out = 0ULL;  in fsi_spi_transfer_data()
376 		u64 in = 0ULL;  in fsi_spi_transfer_data()
423 	u64 clock_cfg = 0ULL;  in fsi_spi_transfer_init()
424 	u64 status = 0ULL;  in fsi_spi_transfer_init()