Lines Matching refs:dws
59 static int dw_spi_debugfs_init(struct dw_spi *dws) in dw_spi_debugfs_init() argument
63 snprintf(name, 32, "dw_spi%d", dws->master->bus_num); in dw_spi_debugfs_init()
64 dws->debugfs = debugfs_create_dir(name, NULL); in dw_spi_debugfs_init()
65 if (!dws->debugfs) in dw_spi_debugfs_init()
68 dws->regset.regs = dw_spi_dbgfs_regs; in dw_spi_debugfs_init()
69 dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs); in dw_spi_debugfs_init()
70 dws->regset.base = dws->regs; in dw_spi_debugfs_init()
71 debugfs_create_regset32("registers", 0400, dws->debugfs, &dws->regset); in dw_spi_debugfs_init()
76 static void dw_spi_debugfs_remove(struct dw_spi *dws) in dw_spi_debugfs_remove() argument
78 debugfs_remove_recursive(dws->debugfs); in dw_spi_debugfs_remove()
82 static inline int dw_spi_debugfs_init(struct dw_spi *dws) in dw_spi_debugfs_init() argument
87 static inline void dw_spi_debugfs_remove(struct dw_spi *dws) in dw_spi_debugfs_remove() argument
94 struct dw_spi *dws = spi_controller_get_devdata(spi->controller); in dw_spi_set_cs() local
105 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select)); in dw_spi_set_cs()
107 dw_writel(dws, DW_SPI_SER, 0); in dw_spi_set_cs()
112 static inline u32 tx_max(struct dw_spi *dws) in tx_max() argument
116 tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR); in tx_max()
126 rxtx_gap = dws->fifo_len - (dws->rx_len - dws->tx_len); in tx_max()
128 return min3((u32)dws->tx_len, tx_room, rxtx_gap); in tx_max()
132 static inline u32 rx_max(struct dw_spi *dws) in rx_max() argument
134 return min_t(u32, dws->rx_len, dw_readl(dws, DW_SPI_RXFLR)); in rx_max()
137 static void dw_writer(struct dw_spi *dws) in dw_writer() argument
139 u32 max = tx_max(dws); in dw_writer()
143 if (dws->tx) { in dw_writer()
144 if (dws->n_bytes == 1) in dw_writer()
145 txw = *(u8 *)(dws->tx); in dw_writer()
147 txw = *(u16 *)(dws->tx); in dw_writer()
149 dws->tx += dws->n_bytes; in dw_writer()
151 dw_write_io_reg(dws, DW_SPI_DR, txw); in dw_writer()
152 --dws->tx_len; in dw_writer()
156 static void dw_reader(struct dw_spi *dws) in dw_reader() argument
158 u32 max = rx_max(dws); in dw_reader()
162 rxw = dw_read_io_reg(dws, DW_SPI_DR); in dw_reader()
163 if (dws->rx) { in dw_reader()
164 if (dws->n_bytes == 1) in dw_reader()
165 *(u8 *)(dws->rx) = rxw; in dw_reader()
167 *(u16 *)(dws->rx) = rxw; in dw_reader()
169 dws->rx += dws->n_bytes; in dw_reader()
171 --dws->rx_len; in dw_reader()
175 int dw_spi_check_status(struct dw_spi *dws, bool raw) in dw_spi_check_status() argument
181 irq_status = dw_readl(dws, DW_SPI_RISR); in dw_spi_check_status()
183 irq_status = dw_readl(dws, DW_SPI_ISR); in dw_spi_check_status()
186 dev_err(&dws->master->dev, "RX FIFO overflow detected\n"); in dw_spi_check_status()
191 dev_err(&dws->master->dev, "RX FIFO underflow detected\n"); in dw_spi_check_status()
196 dev_err(&dws->master->dev, "TX FIFO overflow detected\n"); in dw_spi_check_status()
202 spi_reset_chip(dws); in dw_spi_check_status()
203 if (dws->master->cur_msg) in dw_spi_check_status()
204 dws->master->cur_msg->status = ret; in dw_spi_check_status()
211 static irqreturn_t dw_spi_transfer_handler(struct dw_spi *dws) in dw_spi_transfer_handler() argument
213 u16 irq_status = dw_readl(dws, DW_SPI_ISR); in dw_spi_transfer_handler()
215 if (dw_spi_check_status(dws, false)) { in dw_spi_transfer_handler()
216 spi_finalize_current_transfer(dws->master); in dw_spi_transfer_handler()
227 dw_reader(dws); in dw_spi_transfer_handler()
228 if (!dws->rx_len) { in dw_spi_transfer_handler()
229 spi_mask_intr(dws, 0xff); in dw_spi_transfer_handler()
230 spi_finalize_current_transfer(dws->master); in dw_spi_transfer_handler()
231 } else if (dws->rx_len <= dw_readl(dws, DW_SPI_RXFTLR)) { in dw_spi_transfer_handler()
232 dw_writel(dws, DW_SPI_RXFTLR, dws->rx_len - 1); in dw_spi_transfer_handler()
241 dw_writer(dws); in dw_spi_transfer_handler()
242 if (!dws->tx_len) in dw_spi_transfer_handler()
243 spi_mask_intr(dws, SPI_INT_TXEI); in dw_spi_transfer_handler()
252 struct dw_spi *dws = spi_controller_get_devdata(master); in dw_spi_irq() local
253 u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f; in dw_spi_irq()
259 spi_mask_intr(dws, 0xff); in dw_spi_irq()
263 return dws->transfer_handler(dws); in dw_spi_irq()
266 static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struct spi_device *spi) in dw_spi_prepare_cr0() argument
270 if (!(dws->caps & DW_SPI_CAP_DWC_SSI)) { in dw_spi_prepare_cr0()
299 if (dws->caps & DW_SPI_CAP_KEEMBAY_MST) in dw_spi_prepare_cr0()
306 void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi, in dw_spi_update_config() argument
317 if (!(dws->caps & DW_SPI_CAP_DWC_SSI)) in dw_spi_update_config()
324 dw_writel(dws, DW_SPI_CTRLR0, cr0); in dw_spi_update_config()
327 dw_writel(dws, DW_SPI_CTRLR1, cfg->ndf ? cfg->ndf - 1 : 0); in dw_spi_update_config()
330 clk_div = (DIV_ROUND_UP(dws->max_freq, cfg->freq) + 1) & 0xfffe; in dw_spi_update_config()
331 speed_hz = dws->max_freq / clk_div; in dw_spi_update_config()
333 if (dws->current_freq != speed_hz) { in dw_spi_update_config()
334 spi_set_clk(dws, clk_div); in dw_spi_update_config()
335 dws->current_freq = speed_hz; in dw_spi_update_config()
339 if (dws->cur_rx_sample_dly != chip->rx_sample_dly) { in dw_spi_update_config()
340 dw_writel(dws, DW_SPI_RX_SAMPLE_DLY, chip->rx_sample_dly); in dw_spi_update_config()
341 dws->cur_rx_sample_dly = chip->rx_sample_dly; in dw_spi_update_config()
346 static void dw_spi_irq_setup(struct dw_spi *dws) in dw_spi_irq_setup() argument
356 level = min_t(u16, dws->fifo_len / 2, dws->tx_len); in dw_spi_irq_setup()
357 dw_writel(dws, DW_SPI_TXFTLR, level); in dw_spi_irq_setup()
358 dw_writel(dws, DW_SPI_RXFTLR, level - 1); in dw_spi_irq_setup()
360 dws->transfer_handler = dw_spi_transfer_handler; in dw_spi_irq_setup()
364 spi_umask_intr(dws, imask); in dw_spi_irq_setup()
377 static int dw_spi_poll_transfer(struct dw_spi *dws, in dw_spi_poll_transfer() argument
385 nbits = dws->n_bytes * BITS_PER_BYTE; in dw_spi_poll_transfer()
388 dw_writer(dws); in dw_spi_poll_transfer()
390 delay.value = nbits * (dws->rx_len - dws->tx_len); in dw_spi_poll_transfer()
393 dw_reader(dws); in dw_spi_poll_transfer()
395 ret = dw_spi_check_status(dws, true); in dw_spi_poll_transfer()
398 } while (dws->rx_len); in dw_spi_poll_transfer()
406 struct dw_spi *dws = spi_controller_get_devdata(master); in dw_spi_transfer_one() local
414 dws->dma_mapped = 0; in dw_spi_transfer_one()
415 dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE); in dw_spi_transfer_one()
416 dws->tx = (void *)transfer->tx_buf; in dw_spi_transfer_one()
417 dws->tx_len = transfer->len / dws->n_bytes; in dw_spi_transfer_one()
418 dws->rx = transfer->rx_buf; in dw_spi_transfer_one()
419 dws->rx_len = dws->tx_len; in dw_spi_transfer_one()
424 spi_enable_chip(dws, 0); in dw_spi_transfer_one()
426 dw_spi_update_config(dws, spi, &cfg); in dw_spi_transfer_one()
428 transfer->effective_speed_hz = dws->current_freq; in dw_spi_transfer_one()
432 dws->dma_mapped = master->cur_msg_mapped; in dw_spi_transfer_one()
435 spi_mask_intr(dws, 0xff); in dw_spi_transfer_one()
437 if (dws->dma_mapped) { in dw_spi_transfer_one()
438 ret = dws->dma_ops->dma_setup(dws, transfer); in dw_spi_transfer_one()
443 spi_enable_chip(dws, 1); in dw_spi_transfer_one()
445 if (dws->dma_mapped) in dw_spi_transfer_one()
446 return dws->dma_ops->dma_transfer(dws, transfer); in dw_spi_transfer_one()
447 else if (dws->irq == IRQ_NOTCONNECTED) in dw_spi_transfer_one()
448 return dw_spi_poll_transfer(dws, transfer); in dw_spi_transfer_one()
450 dw_spi_irq_setup(dws); in dw_spi_transfer_one()
458 struct dw_spi *dws = spi_controller_get_devdata(master); in dw_spi_handle_err() local
460 if (dws->dma_mapped) in dw_spi_handle_err()
461 dws->dma_ops->dma_stop(dws); in dw_spi_handle_err()
463 spi_reset_chip(dws); in dw_spi_handle_err()
484 static int dw_spi_init_mem_buf(struct dw_spi *dws, const struct spi_mem_op *op) in dw_spi_init_mem_buf() argument
498 out = dws->buf; in dw_spi_init_mem_buf()
520 dws->n_bytes = 1; in dw_spi_init_mem_buf()
521 dws->tx = out; in dw_spi_init_mem_buf()
522 dws->tx_len = len; in dw_spi_init_mem_buf()
524 dws->rx = op->data.buf.in; in dw_spi_init_mem_buf()
525 dws->rx_len = op->data.nbytes; in dw_spi_init_mem_buf()
527 dws->rx = NULL; in dw_spi_init_mem_buf()
528 dws->rx_len = 0; in dw_spi_init_mem_buf()
534 static void dw_spi_free_mem_buf(struct dw_spi *dws) in dw_spi_free_mem_buf() argument
536 if (dws->tx != dws->buf) in dw_spi_free_mem_buf()
537 kfree(dws->tx); in dw_spi_free_mem_buf()
540 static int dw_spi_write_then_read(struct dw_spi *dws, struct spi_device *spi) in dw_spi_write_then_read() argument
551 len = min(dws->fifo_len, dws->tx_len); in dw_spi_write_then_read()
552 buf = dws->tx; in dw_spi_write_then_read()
554 dw_write_io_reg(dws, DW_SPI_DR, *buf++); in dw_spi_write_then_read()
562 len = dws->tx_len - ((void *)buf - dws->tx); in dw_spi_write_then_read()
565 entries = readl_relaxed(dws->regs + DW_SPI_TXFLR); in dw_spi_write_then_read()
567 dev_err(&dws->master->dev, "CS de-assertion on Tx\n"); in dw_spi_write_then_read()
570 room = min(dws->fifo_len - entries, len); in dw_spi_write_then_read()
572 dw_write_io_reg(dws, DW_SPI_DR, *buf++); in dw_spi_write_then_read()
580 len = dws->rx_len; in dw_spi_write_then_read()
581 buf = dws->rx; in dw_spi_write_then_read()
583 entries = readl_relaxed(dws->regs + DW_SPI_RXFLR); in dw_spi_write_then_read()
585 sts = readl_relaxed(dws->regs + DW_SPI_RISR); in dw_spi_write_then_read()
587 dev_err(&dws->master->dev, "FIFO overflow on Rx\n"); in dw_spi_write_then_read()
594 *buf++ = dw_read_io_reg(dws, DW_SPI_DR); in dw_spi_write_then_read()
600 static inline bool dw_spi_ctlr_busy(struct dw_spi *dws) in dw_spi_ctlr_busy() argument
602 return dw_readl(dws, DW_SPI_SR) & SR_BUSY; in dw_spi_ctlr_busy()
605 static int dw_spi_wait_mem_op_done(struct dw_spi *dws) in dw_spi_wait_mem_op_done() argument
612 nents = dw_readl(dws, DW_SPI_TXFLR); in dw_spi_wait_mem_op_done()
613 ns = NSEC_PER_SEC / dws->current_freq * nents; in dw_spi_wait_mem_op_done()
614 ns *= dws->n_bytes * BITS_PER_BYTE; in dw_spi_wait_mem_op_done()
624 while (dw_spi_ctlr_busy(dws) && retry--) in dw_spi_wait_mem_op_done()
628 dev_err(&dws->master->dev, "Mem op hanged up\n"); in dw_spi_wait_mem_op_done()
635 static void dw_spi_stop_mem_op(struct dw_spi *dws, struct spi_device *spi) in dw_spi_stop_mem_op() argument
637 spi_enable_chip(dws, 0); in dw_spi_stop_mem_op()
639 spi_enable_chip(dws, 1); in dw_spi_stop_mem_op()
652 struct dw_spi *dws = spi_controller_get_devdata(mem->spi->controller); in dw_spi_exec_mem_op() local
661 ret = dw_spi_init_mem_buf(dws, op); in dw_spi_exec_mem_op()
670 cfg.freq = clamp(mem->spi->max_speed_hz, 0U, dws->max_mem_freq); in dw_spi_exec_mem_op()
678 spi_enable_chip(dws, 0); in dw_spi_exec_mem_op()
680 dw_spi_update_config(dws, mem->spi, &cfg); in dw_spi_exec_mem_op()
682 spi_mask_intr(dws, 0xff); in dw_spi_exec_mem_op()
684 spi_enable_chip(dws, 1); in dw_spi_exec_mem_op()
717 ret = dw_spi_write_then_read(dws, mem->spi); in dw_spi_exec_mem_op()
730 ret = dw_spi_wait_mem_op_done(dws); in dw_spi_exec_mem_op()
732 ret = dw_spi_check_status(dws, true); in dw_spi_exec_mem_op()
735 dw_spi_stop_mem_op(dws, mem->spi); in dw_spi_exec_mem_op()
737 dw_spi_free_mem_buf(dws); in dw_spi_exec_mem_op()
751 static void dw_spi_init_mem_ops(struct dw_spi *dws) in dw_spi_init_mem_ops() argument
753 if (!dws->mem_ops.exec_op && !(dws->caps & DW_SPI_CAP_CS_OVERRIDE) && in dw_spi_init_mem_ops()
754 !dws->set_cs) { in dw_spi_init_mem_ops()
755 dws->mem_ops.adjust_op_size = dw_spi_adjust_mem_op_size; in dw_spi_init_mem_ops()
756 dws->mem_ops.supports_op = dw_spi_supports_mem_op; in dw_spi_init_mem_ops()
757 dws->mem_ops.exec_op = dw_spi_exec_mem_op; in dw_spi_init_mem_ops()
758 if (!dws->max_mem_freq) in dw_spi_init_mem_ops()
759 dws->max_mem_freq = dws->max_freq; in dw_spi_init_mem_ops()
766 struct dw_spi *dws = spi_controller_get_devdata(spi->controller); in dw_spi_setup() local
772 struct dw_spi *dws = spi_controller_get_devdata(spi->controller); in dw_spi_setup() local
784 rx_sample_dly_ns = dws->def_rx_sample_dly_ns; in dw_spi_setup()
787 dws->max_freq); in dw_spi_setup()
795 chip->cr0 = dw_spi_prepare_cr0(dws, spi); in dw_spi_setup()
809 static void spi_hw_init(struct device *dev, struct dw_spi *dws) in spi_hw_init() argument
811 spi_reset_chip(dws); in spi_hw_init()
817 if (!dws->fifo_len) { in spi_hw_init()
821 dw_writel(dws, DW_SPI_TXFTLR, fifo); in spi_hw_init()
822 if (fifo != dw_readl(dws, DW_SPI_TXFTLR)) in spi_hw_init()
825 dw_writel(dws, DW_SPI_TXFTLR, 0); in spi_hw_init()
827 dws->fifo_len = (fifo == 1) ? 0 : fifo; in spi_hw_init()
828 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len); in spi_hw_init()
832 if (dws->caps & DW_SPI_CAP_CS_OVERRIDE) in spi_hw_init()
833 dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF); in spi_hw_init()
836 int dw_spi_add_host(struct device *dev, struct dw_spi *dws) in dw_spi_add_host() argument
841 if (!dws) in dw_spi_add_host()
848 dws->master = master; in dw_spi_add_host()
849 dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR); in dw_spi_add_host()
851 spi_controller_set_devdata(master, dws); in dw_spi_add_host()
854 spi_hw_init(dev, dws); in dw_spi_add_host()
856 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev), in dw_spi_add_host()
863 dw_spi_init_mem_ops(dws); in dw_spi_add_host()
868 master->bus_num = dws->bus_num; in dw_spi_add_host()
869 master->num_chipselect = dws->num_cs; in dw_spi_add_host()
872 if (dws->set_cs) in dw_spi_add_host()
873 master->set_cs = dws->set_cs; in dw_spi_add_host()
878 if (dws->mem_ops.exec_op) in dw_spi_add_host()
879 master->mem_ops = &dws->mem_ops; in dw_spi_add_host()
880 master->max_speed_hz = dws->max_freq; in dw_spi_add_host()
888 &dws->def_rx_sample_dly_ns); in dw_spi_add_host()
890 if (dws->dma_ops && dws->dma_ops->dma_init) { in dw_spi_add_host()
891 ret = dws->dma_ops->dma_init(dev, dws); in dw_spi_add_host()
895 master->can_dma = dws->dma_ops->can_dma; in dw_spi_add_host()
906 dw_spi_debugfs_init(dws); in dw_spi_add_host()
910 if (dws->dma_ops && dws->dma_ops->dma_exit) in dw_spi_add_host()
911 dws->dma_ops->dma_exit(dws); in dw_spi_add_host()
912 spi_enable_chip(dws, 0); in dw_spi_add_host()
913 free_irq(dws->irq, master); in dw_spi_add_host()
920 void dw_spi_remove_host(struct dw_spi *dws) in dw_spi_remove_host() argument
922 dw_spi_debugfs_remove(dws); in dw_spi_remove_host()
924 spi_unregister_controller(dws->master); in dw_spi_remove_host()
926 if (dws->dma_ops && dws->dma_ops->dma_exit) in dw_spi_remove_host()
927 dws->dma_ops->dma_exit(dws); in dw_spi_remove_host()
929 spi_shutdown_chip(dws); in dw_spi_remove_host()
931 free_irq(dws->irq, dws->master); in dw_spi_remove_host()
935 int dw_spi_suspend_host(struct dw_spi *dws) in dw_spi_suspend_host() argument
939 ret = spi_controller_suspend(dws->master); in dw_spi_suspend_host()
943 spi_shutdown_chip(dws); in dw_spi_suspend_host()
948 int dw_spi_resume_host(struct dw_spi *dws) in dw_spi_resume_host() argument
950 spi_hw_init(&dws->master->dev, dws); in dw_spi_resume_host()
951 return spi_controller_resume(dws->master); in dw_spi_resume_host()