122 static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data)  in spireg_write()  function
133 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_auto_cs_unset()
142 	spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);  in a3700_spi_activate_cs()
152 	spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);  in a3700_spi_deactivate_cs()
181 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_pin_mode_set()
195 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_fifo_mode_set()
215 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_mode_set()
237 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_clock_set()
242 		spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val);  in a3700_spi_clock_set()
255 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_bytelen_set()
267 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_fifo_flush()
288 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_init()
294 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_init()
308 	spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);  in a3700_spi_init()
309 	spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0);  in a3700_spi_init()
312 	spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);  in a3700_spi_init()
313 	spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U);  in a3700_spi_init()
331 	spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);  in a3700_spi_interrupt()
332 	spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause);  in a3700_spi_interrupt()
361 	spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG,  in a3700_spi_wait_completion()
385 	spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);  in a3700_spi_wait_completion()
412 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_fifo_thres_set()
451 	spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0);  in a3700_spi_header_set()
452 	spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0);  in a3700_spi_header_set()
453 	spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0);  in a3700_spi_header_set()
454 	spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);  in a3700_spi_header_set()
470 			spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val);  in a3700_spi_header_set()
481 			spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val);  in a3700_spi_header_set()
500 		spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);  in a3700_spi_fifo_write()
553 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_transfer_abort_fifo()
565 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_transfer_abort_fifo()
624 		spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, 0);  in a3700_spi_transfer_one_fifo()
627 		spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG,  in a3700_spi_transfer_one_fifo()
633 		spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_transfer_one_fifo()
638 		spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_transfer_one_fifo()
712 		spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_transfer_one_fifo()
729 	spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);  in a3700_spi_transfer_one_fifo()
763 		spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);  in a3700_spi_transfer_one_full_duplex()