Lines Matching refs:a3700_spi
102 struct a3700_spi { struct
117 static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset) in spireg_read() argument
119 return readl(a3700_spi->base + offset); in spireg_read()
122 static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data) in spireg_write() argument
124 writel(data, a3700_spi->base + offset); in spireg_write()
127 static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi) in a3700_spi_auto_cs_unset() argument
131 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_auto_cs_unset()
133 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_auto_cs_unset()
136 static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs) in a3700_spi_activate_cs() argument
140 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); in a3700_spi_activate_cs()
142 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); in a3700_spi_activate_cs()
145 static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi, in a3700_spi_deactivate_cs() argument
150 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); in a3700_spi_deactivate_cs()
152 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); in a3700_spi_deactivate_cs()
155 static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi, in a3700_spi_pin_mode_set() argument
160 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_pin_mode_set()
177 dev_err(&a3700_spi->master->dev, "wrong pin mode %u", pin_mode); in a3700_spi_pin_mode_set()
181 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_pin_mode_set()
186 static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi, bool enable) in a3700_spi_fifo_mode_set() argument
190 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_fifo_mode_set()
195 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_fifo_mode_set()
198 static void a3700_spi_mode_set(struct a3700_spi *a3700_spi, in a3700_spi_mode_set() argument
203 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_mode_set()
215 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_mode_set()
218 static void a3700_spi_clock_set(struct a3700_spi *a3700_spi, in a3700_spi_clock_set() argument
224 prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz); in a3700_spi_clock_set()
233 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_clock_set()
237 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_clock_set()
240 val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG); in a3700_spi_clock_set()
242 spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val); in a3700_spi_clock_set()
246 static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len) in a3700_spi_bytelen_set() argument
250 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_bytelen_set()
255 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_bytelen_set()
257 a3700_spi->byte_len = len; in a3700_spi_bytelen_set()
260 static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi) in a3700_spi_fifo_flush() argument
265 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_fifo_flush()
267 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_fifo_flush()
270 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_fifo_flush()
279 static void a3700_spi_init(struct a3700_spi *a3700_spi) in a3700_spi_init() argument
281 struct spi_master *master = a3700_spi->master; in a3700_spi_init()
286 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_init()
288 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_init()
292 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_init()
294 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_init()
297 a3700_spi_auto_cs_unset(a3700_spi); in a3700_spi_init()
299 a3700_spi_deactivate_cs(a3700_spi, i); in a3700_spi_init()
302 a3700_spi_fifo_mode_set(a3700_spi, true); in a3700_spi_init()
305 a3700_spi_mode_set(a3700_spi, master->mode_bits); in a3700_spi_init()
308 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); in a3700_spi_init()
309 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0); in a3700_spi_init()
312 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); in a3700_spi_init()
313 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U); in a3700_spi_init()
319 struct a3700_spi *a3700_spi; in a3700_spi_interrupt() local
322 a3700_spi = spi_master_get_devdata(master); in a3700_spi_interrupt()
325 cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG); in a3700_spi_interrupt()
327 if (!cause || !(a3700_spi->wait_mask & cause)) in a3700_spi_interrupt()
331 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); in a3700_spi_interrupt()
332 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause); in a3700_spi_interrupt()
335 complete(&a3700_spi->done); in a3700_spi_interrupt()
342 struct a3700_spi *a3700_spi; in a3700_spi_wait_completion() local
347 a3700_spi = spi_master_get_devdata(spi->master); in a3700_spi_wait_completion()
355 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); in a3700_spi_wait_completion()
356 if (a3700_spi->wait_mask & ctrl_reg) in a3700_spi_wait_completion()
359 reinit_completion(&a3700_spi->done); in a3700_spi_wait_completion()
361 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, in a3700_spi_wait_completion()
362 a3700_spi->wait_mask); in a3700_spi_wait_completion()
365 timeout = wait_for_completion_timeout(&a3700_spi->done, in a3700_spi_wait_completion()
368 a3700_spi->wait_mask = 0; in a3700_spi_wait_completion()
381 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); in a3700_spi_wait_completion()
382 if (a3700_spi->wait_mask & ctrl_reg) in a3700_spi_wait_completion()
385 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); in a3700_spi_wait_completion()
394 struct a3700_spi *a3700_spi; in a3700_spi_transfer_wait() local
396 a3700_spi = spi_master_get_devdata(spi->master); in a3700_spi_transfer_wait()
397 a3700_spi->wait_mask = bit_mask; in a3700_spi_transfer_wait()
402 static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi, in a3700_spi_fifo_thres_set() argument
407 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_fifo_thres_set()
412 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_fifo_thres_set()
418 struct a3700_spi *a3700_spi; in a3700_spi_transfer_setup() local
420 a3700_spi = spi_master_get_devdata(spi->master); in a3700_spi_transfer_setup()
422 a3700_spi_clock_set(a3700_spi, xfer->speed_hz); in a3700_spi_transfer_setup()
427 a3700_spi_bytelen_set(a3700_spi, 4); in a3700_spi_transfer_setup()
430 a3700_spi->tx_buf = xfer->tx_buf; in a3700_spi_transfer_setup()
431 a3700_spi->rx_buf = xfer->rx_buf; in a3700_spi_transfer_setup()
432 a3700_spi->buf_len = xfer->len; in a3700_spi_transfer_setup()
437 struct a3700_spi *a3700_spi = spi_master_get_devdata(spi->master); in a3700_spi_set_cs() local
440 a3700_spi_activate_cs(a3700_spi, spi->chip_select); in a3700_spi_set_cs()
442 a3700_spi_deactivate_cs(a3700_spi, spi->chip_select); in a3700_spi_set_cs()
445 static void a3700_spi_header_set(struct a3700_spi *a3700_spi) in a3700_spi_header_set() argument
451 spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0); in a3700_spi_header_set()
452 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0); in a3700_spi_header_set()
453 spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0); in a3700_spi_header_set()
454 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); in a3700_spi_header_set()
457 if (a3700_spi->tx_buf) { in a3700_spi_header_set()
466 addr_cnt = a3700_spi->buf_len % 4; in a3700_spi_header_set()
470 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val); in a3700_spi_header_set()
473 a3700_spi->buf_len -= addr_cnt; in a3700_spi_header_set()
478 val = (val << 8) | a3700_spi->tx_buf[0]; in a3700_spi_header_set()
479 a3700_spi->tx_buf++; in a3700_spi_header_set()
481 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val); in a3700_spi_header_set()
486 static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi) in a3700_is_wfifo_full() argument
490 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); in a3700_is_wfifo_full()
494 static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi) in a3700_spi_fifo_write() argument
498 while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) { in a3700_spi_fifo_write()
499 val = *(u32 *)a3700_spi->tx_buf; in a3700_spi_fifo_write()
500 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val); in a3700_spi_fifo_write()
501 a3700_spi->buf_len -= 4; in a3700_spi_fifo_write()
502 a3700_spi->tx_buf += 4; in a3700_spi_fifo_write()
508 static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi) in a3700_is_rfifo_empty() argument
510 u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); in a3700_is_rfifo_empty()
515 static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi) in a3700_spi_fifo_read() argument
519 while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) { in a3700_spi_fifo_read()
520 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); in a3700_spi_fifo_read()
521 if (a3700_spi->buf_len >= 4) { in a3700_spi_fifo_read()
523 memcpy(a3700_spi->rx_buf, &val, 4); in a3700_spi_fifo_read()
525 a3700_spi->buf_len -= 4; in a3700_spi_fifo_read()
526 a3700_spi->rx_buf += 4; in a3700_spi_fifo_read()
533 while (a3700_spi->buf_len) { in a3700_spi_fifo_read()
534 *a3700_spi->rx_buf = val & 0xff; in a3700_spi_fifo_read()
537 a3700_spi->buf_len--; in a3700_spi_fifo_read()
538 a3700_spi->rx_buf++; in a3700_spi_fifo_read()
546 static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi) in a3700_spi_transfer_abort_fifo() argument
551 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_transfer_abort_fifo()
553 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_transfer_abort_fifo()
556 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_transfer_abort_fifo()
562 a3700_spi_fifo_flush(a3700_spi); in a3700_spi_transfer_abort_fifo()
565 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_transfer_abort_fifo()
571 struct a3700_spi *a3700_spi = spi_master_get_devdata(master); in a3700_spi_prepare_message() local
575 ret = clk_enable(a3700_spi->clk); in a3700_spi_prepare_message()
582 ret = a3700_spi_fifo_flush(a3700_spi); in a3700_spi_prepare_message()
586 a3700_spi_mode_set(a3700_spi, spi->mode); in a3700_spi_prepare_message()
595 struct a3700_spi *a3700_spi = spi_master_get_devdata(master); in a3700_spi_transfer_one_fifo() local
601 a3700_spi_fifo_mode_set(a3700_spi, true); in a3700_spi_transfer_one_fifo()
605 a3700_spi_fifo_thres_set(a3700_spi, byte_len); in a3700_spi_transfer_one_fifo()
612 a3700_spi_pin_mode_set(a3700_spi, nbits, xfer->rx_buf ? true : false); in a3700_spi_transfer_one_fifo()
615 a3700_spi_fifo_flush(a3700_spi); in a3700_spi_transfer_one_fifo()
618 a3700_spi_header_set(a3700_spi); in a3700_spi_transfer_one_fifo()
624 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, 0); in a3700_spi_transfer_one_fifo()
627 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, in a3700_spi_transfer_one_fifo()
628 a3700_spi->buf_len); in a3700_spi_transfer_one_fifo()
630 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_transfer_one_fifo()
633 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_transfer_one_fifo()
636 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_transfer_one_fifo()
638 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_transfer_one_fifo()
646 a3700_spi->xmit_data = (a3700_spi->buf_len != 0); in a3700_spi_transfer_one_fifo()
649 while (a3700_spi->buf_len) { in a3700_spi_transfer_one_fifo()
650 if (a3700_spi->tx_buf) { in a3700_spi_transfer_one_fifo()
660 ret = a3700_spi_fifo_write(a3700_spi); in a3700_spi_transfer_one_fifo()
663 } else if (a3700_spi->rx_buf) { in a3700_spi_transfer_one_fifo()
673 ret = a3700_spi_fifo_read(a3700_spi); in a3700_spi_transfer_one_fifo()
691 if (a3700_spi->tx_buf) { in a3700_spi_transfer_one_fifo()
692 if (a3700_spi->xmit_data) { in a3700_spi_transfer_one_fifo()
710 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_transfer_one_fifo()
712 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_transfer_one_fifo()
716 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); in a3700_spi_transfer_one_fifo()
729 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); in a3700_spi_transfer_one_fifo()
733 a3700_spi_transfer_abort_fifo(a3700_spi); in a3700_spi_transfer_one_fifo()
744 struct a3700_spi *a3700_spi = spi_master_get_devdata(master); in a3700_spi_transfer_one_full_duplex() local
748 a3700_spi_fifo_mode_set(a3700_spi, false); in a3700_spi_transfer_one_full_duplex()
750 while (a3700_spi->buf_len) { in a3700_spi_transfer_one_full_duplex()
755 if (a3700_spi->buf_len < 4) in a3700_spi_transfer_one_full_duplex()
756 a3700_spi_bytelen_set(a3700_spi, 1); in a3700_spi_transfer_one_full_duplex()
758 if (a3700_spi->byte_len == 1) in a3700_spi_transfer_one_full_duplex()
759 val = *a3700_spi->tx_buf; in a3700_spi_transfer_one_full_duplex()
761 val = *(u32 *)a3700_spi->tx_buf; in a3700_spi_transfer_one_full_duplex()
763 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val); in a3700_spi_transfer_one_full_duplex()
766 while (!(spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG) & in a3700_spi_transfer_one_full_duplex()
770 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); in a3700_spi_transfer_one_full_duplex()
772 memcpy(a3700_spi->rx_buf, &val, a3700_spi->byte_len); in a3700_spi_transfer_one_full_duplex()
774 a3700_spi->buf_len -= a3700_spi->byte_len; in a3700_spi_transfer_one_full_duplex()
775 a3700_spi->tx_buf += a3700_spi->byte_len; in a3700_spi_transfer_one_full_duplex()
776 a3700_spi->rx_buf += a3700_spi->byte_len; in a3700_spi_transfer_one_full_duplex()
800 struct a3700_spi *a3700_spi = spi_master_get_devdata(master); in a3700_spi_unprepare_message() local
802 clk_disable(a3700_spi->clk); in a3700_spi_unprepare_message()
819 struct a3700_spi *spi; in a3700_spi_probe()
914 struct a3700_spi *spi = spi_master_get_devdata(master); in a3700_spi_remove()