443 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,  in tegra_pmc_writel()  function
476 		tegra_pmc_writel(pmc, value, offset);  in tegra_pmc_scratch_writel()
535 		tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);  in tegra20_powergate_set()
562 	tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);  in tegra114_powergate_set()
620 			tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);  in __tegra_powergate_remove_clamping()
636 	tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);  in __tegra_powergate_remove_clamping()
988 	tegra_pmc_writel(pmc, value, PMC_CNTRL);  in tegra_pmc_restart_notify()
1315 		tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);  in tegra_io_pad_prepare()
1320 		tegra_pmc_writel(pmc, value, SEL_DPD_TIM);  in tegra_io_pad_prepare()
1347 		tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);  in tegra_io_pad_unprepare()
1370 	tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);  in tegra_io_pad_power_enable()
1406 	tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);  in tegra_io_pad_power_disable()
1461 		tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);  in tegra_io_pad_set_voltage()
1466 		tegra_pmc_writel(pmc, value, PMC_PWR_DET);  in tegra_io_pad_set_voltage()
1476 		tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);  in tegra_io_pad_set_voltage()
1571 	tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);  in tegra_pmc_enter_suspend_mode()
1575 	tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);  in tegra_pmc_enter_suspend_mode()
1580 	tegra_pmc_writel(pmc, value, PMC_CNTRL);  in tegra_pmc_enter_suspend_mode()
1704 	tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);  in tegra_pmc_init_tsense_reset()
1708 	tegra_pmc_writel(pmc, value, PMC_SCRATCH54);  in tegra_pmc_init_tsense_reset()
1726 	tegra_pmc_writel(pmc, value, PMC_SCRATCH55);  in tegra_pmc_init_tsense_reset()
1730 	tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);  in tegra_pmc_init_tsense_reset()
2039 	tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);  in tegra210_pmc_irq_set_wake()
2040 	tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);  in tegra210_pmc_irq_set_wake()
2042 	tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);  in tegra210_pmc_irq_set_wake()
2043 	tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);  in tegra210_pmc_irq_set_wake()
2058 	tegra_pmc_writel(pmc, value, offset);  in tegra210_pmc_irq_set_wake()
2098 	tegra_pmc_writel(pmc, value, offset);  in tegra210_pmc_irq_set_type()
2275 	tegra_pmc_writel(pmc, val, clk->offs);  in pmc_clk_mux_set_parent()
2297 	tegra_pmc_writel(pmc, val, offs);  in pmc_clk_set_state()
2460 		tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);  in tegra_pmc_clock_register()
2643 	tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);  in tegra_pmc_suspend()
2652 	tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);  in tegra_pmc_resume()
2691 	tegra_pmc_writel(pmc, value, PMC_CNTRL);  in tegra20_pmc_init()
2706 	tegra_pmc_writel(pmc, value, PMC_CNTRL);  in tegra20_pmc_init()
2711 	tegra_pmc_writel(pmc, value, PMC_CNTRL);  in tegra20_pmc_init()
2718 		tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),  in tegra20_pmc_init()
2720 		tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);  in tegra20_pmc_init()
2737 	tegra_pmc_writel(pmc, value, PMC_CNTRL);  in tegra20_pmc_setup_irq_polarity()