Lines Matching +full:rk3399 +full:- +full:vdec
1 // SPDX-License-Identifier: GPL-2.0-only
26 #include <dt-bindings/power/px30-power.h>
27 #include <dt-bindings/power/rv1126-power.h>
28 #include <dt-bindings/power/rk1808-power.h>
29 #include <dt-bindings/power/rk3036-power.h>
30 #include <dt-bindings/power/rk3066-power.h>
31 #include <dt-bindings/power/rk3128-power.h>
32 #include <dt-bindings/power/rk3188-power.h>
33 #include <dt-bindings/power/rk3228-power.h>
34 #include <dt-bindings/power/rk3288-power.h>
35 #include <dt-bindings/power/rk3328-power.h>
36 #include <dt-bindings/power/rk3366-power.h>
37 #include <dt-bindings/power/rk3368-power.h>
38 #include <dt-bindings/power/rk3399-power.h>
39 #include <dt-bindings/power/rk3528-power.h>
40 #include <dt-bindings/power/rk3562-power.h>
41 #include <dt-bindings/power/rk3568-power.h>
42 #include <dt-bindings/power/rk3588-power.h>
159 mutex_lock(&pd->pmu->mutex); in rockchip_pmu_lock()
166 mutex_unlock(&pd->pmu->mutex); in rockchip_pmu_unlock()
332 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_idle()
333 const struct rockchip_domain_info *pd_info = pd->info; in rockchip_pmu_domain_is_idle()
336 regmap_read(pmu->regmap, pmu->info->idle_offset, &val); in rockchip_pmu_domain_is_idle()
337 return (val & pd_info->idle_mask) == pd_info->idle_mask; in rockchip_pmu_domain_is_idle()
344 regmap_read(pmu->regmap, pmu->info->ack_offset, &val); in rockchip_pmu_read_ack()
350 const struct rockchip_domain_info *pd_info = pd->info; in rockchip_pmu_ungate_clk()
351 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_ungate_clk()
354 if (!pd_info->clk_ungate_mask) in rockchip_pmu_ungate_clk()
356 if (!pmu->info->clk_ungate_offset) in rockchip_pmu_ungate_clk()
359 val = ungate ? (pd_info->clk_ungate_mask | pd_info->clk_ungate_w_mask) : in rockchip_pmu_ungate_clk()
360 pd_info->clk_ungate_w_mask; in rockchip_pmu_ungate_clk()
361 regmap_write(pmu->regmap, pmu->info->clk_ungate_offset, val); in rockchip_pmu_ungate_clk()
368 const struct rockchip_domain_info *pd_info = pd->info; in rockchip_pmu_mem_shut_down()
369 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_mem_shut_down()
372 if (!pd_info->mem_num) in rockchip_pmu_mem_shut_down()
374 if (!pmu->info->mem_sd_offset) in rockchip_pmu_mem_shut_down()
377 for (i = 0; i < pd_info->mem_num; i++) in rockchip_pmu_mem_shut_down()
378 regmap_write(pmu->regmap, pmu->info->mem_sd_offset, in rockchip_pmu_mem_shut_down()
387 const struct rockchip_domain_info *pd_info = pd->info; in rockchip_pmu_set_idle_request()
388 struct generic_pm_domain *genpd = &pd->genpd; in rockchip_pmu_set_idle_request()
389 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_set_idle_request()
396 if (pd_info->req_offset) in rockchip_pmu_set_idle_request()
397 pd_req_offset = pd_info->req_offset; in rockchip_pmu_set_idle_request()
399 if (pd_info->req_mask == 0) in rockchip_pmu_set_idle_request()
401 else if (pd_info->req_w_mask) in rockchip_pmu_set_idle_request()
402 regmap_write(pmu->regmap, pmu->info->req_offset + pd_req_offset, in rockchip_pmu_set_idle_request()
403 idle ? (pd_info->req_mask | pd_info->req_w_mask) : in rockchip_pmu_set_idle_request()
404 pd_info->req_w_mask); in rockchip_pmu_set_idle_request()
406 regmap_update_bits(pmu->regmap, pmu->info->req_offset + in rockchip_pmu_set_idle_request()
407 pd_req_offset, pd_info->req_mask, in rockchip_pmu_set_idle_request()
408 idle ? -1U : 0); in rockchip_pmu_set_idle_request()
413 target_ack = idle ? pd_info->ack_mask : 0; in rockchip_pmu_set_idle_request()
415 (val & pd_info->ack_mask) == target_ack, in rockchip_pmu_set_idle_request()
418 dev_err(pmu->dev, in rockchip_pmu_set_idle_request()
420 genpd->name, idle, target_ack, val); in rockchip_pmu_set_idle_request()
427 dev_err(pmu->dev, in rockchip_pmu_set_idle_request()
429 genpd->name, idle, is_idle); in rockchip_pmu_set_idle_request()
446 return -EINVAL; in rockchip_pmu_idle_request()
448 if (IS_ERR_OR_NULL(dev->pm_domain)) in rockchip_pmu_idle_request()
449 return -EINVAL; in rockchip_pmu_idle_request()
451 genpd = pd_to_genpd(dev->pm_domain); in rockchip_pmu_idle_request()
466 for (i = 0; i < pd->num_qos; i++) { in rockchip_pmu_save_qos()
467 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
469 &pd->qos_save_regs[0][i]); in rockchip_pmu_save_qos()
470 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
472 &pd->qos_save_regs[1][i]); in rockchip_pmu_save_qos()
473 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
475 &pd->qos_save_regs[2][i]); in rockchip_pmu_save_qos()
476 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
478 &pd->qos_save_regs[3][i]); in rockchip_pmu_save_qos()
479 regmap_read(pd->qos_regmap[i], in rockchip_pmu_save_qos()
481 &pd->qos_save_regs[4][i]); in rockchip_pmu_save_qos()
490 for (i = 0; i < pd->num_qos; i++) { in rockchip_pmu_restore_qos()
491 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
493 pd->qos_save_regs[0][i]); in rockchip_pmu_restore_qos()
494 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
496 pd->qos_save_regs[1][i]); in rockchip_pmu_restore_qos()
497 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
499 pd->qos_save_regs[2][i]); in rockchip_pmu_restore_qos()
500 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
502 pd->qos_save_regs[3][i]); in rockchip_pmu_restore_qos()
503 regmap_write(pd->qos_regmap[i], in rockchip_pmu_restore_qos()
505 pd->qos_save_regs[4][i]); in rockchip_pmu_restore_qos()
515 if (!pd->is_qos_need_init) in rockchip_pmu_init_qos()
518 for (i = 0; i < pd->num_qos; i++) { in rockchip_pmu_init_qos()
519 if (pd->qos_is_need_init[0][i]) in rockchip_pmu_init_qos()
520 regmap_write(pd->qos_regmap[i], in rockchip_pmu_init_qos()
522 pd->qos_save_regs[0][i]); in rockchip_pmu_init_qos()
524 if (pd->qos_is_need_init[1][i]) in rockchip_pmu_init_qos()
525 regmap_write(pd->qos_regmap[i], in rockchip_pmu_init_qos()
527 pd->qos_save_regs[1][i]); in rockchip_pmu_init_qos()
529 if (pd->qos_is_need_init[2][i]) in rockchip_pmu_init_qos()
530 regmap_write(pd->qos_regmap[i], in rockchip_pmu_init_qos()
532 pd->qos_save_regs[2][i]); in rockchip_pmu_init_qos()
534 if (pd->qos_is_need_init[3][i]) in rockchip_pmu_init_qos()
535 regmap_write(pd->qos_regmap[i], in rockchip_pmu_init_qos()
537 pd->qos_save_regs[3][i]); in rockchip_pmu_init_qos()
539 if (pd->qos_is_need_init[4][i]) in rockchip_pmu_init_qos()
540 regmap_write(pd->qos_regmap[i], in rockchip_pmu_init_qos()
542 pd->qos_save_regs[4][i]); in rockchip_pmu_init_qos()
545 kfree(pd->qos_is_need_init[0]); in rockchip_pmu_init_qos()
546 pd->qos_is_need_init[0] = NULL; in rockchip_pmu_init_qos()
547 pd->is_qos_need_init = false; in rockchip_pmu_init_qos()
557 return -EINVAL; in rockchip_save_qos()
559 if (IS_ERR_OR_NULL(dev->pm_domain)) in rockchip_save_qos()
560 return -EINVAL; in rockchip_save_qos()
562 genpd = pd_to_genpd(dev->pm_domain); in rockchip_save_qos()
580 return -EINVAL; in rockchip_restore_qos()
582 if (IS_ERR_OR_NULL(dev->pm_domain)) in rockchip_restore_qos()
583 return -EINVAL; in rockchip_restore_qos()
585 genpd = pd_to_genpd(dev->pm_domain); in rockchip_restore_qos()
598 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_mem_on()
601 regmap_read(pmu->regmap, in rockchip_pmu_domain_is_mem_on()
602 pmu->info->mem_status_offset + pd->info->mem_offset, &val); in rockchip_pmu_domain_is_mem_on()
605 return !(val & pd->info->mem_status_mask); in rockchip_pmu_domain_is_mem_on()
610 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_chain_on()
613 regmap_read(pmu->regmap, in rockchip_pmu_domain_is_chain_on()
614 pmu->info->chain_status_offset + pd->info->mem_offset, &val); in rockchip_pmu_domain_is_chain_on()
617 return val & pd->info->mem_status_mask; in rockchip_pmu_domain_is_chain_on()
622 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_mem_reset()
623 struct generic_pm_domain *genpd = &pd->genpd; in rockchip_pmu_domain_mem_reset()
630 dev_err(pmu->dev, in rockchip_pmu_domain_mem_reset()
632 genpd->name, is_on); in rockchip_pmu_domain_mem_reset()
638 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, in rockchip_pmu_domain_mem_reset()
639 (pd->info->pwr_mask | pd->info->pwr_w_mask)); in rockchip_pmu_domain_mem_reset()
645 dev_err(pmu->dev, in rockchip_pmu_domain_mem_reset()
647 genpd->name, is_on); in rockchip_pmu_domain_mem_reset()
651 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, in rockchip_pmu_domain_mem_reset()
652 pd->info->pwr_w_mask); in rockchip_pmu_domain_mem_reset()
658 dev_err(pmu->dev, in rockchip_pmu_domain_mem_reset()
660 genpd->name, is_on); in rockchip_pmu_domain_mem_reset()
670 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pmu_domain_is_on()
673 if (pd->info->repair_status_mask) { in rockchip_pmu_domain_is_on()
674 regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val); in rockchip_pmu_domain_is_on()
676 return val & pd->info->repair_status_mask; in rockchip_pmu_domain_is_on()
679 /* check idle status for idle-only domains */ in rockchip_pmu_domain_is_on()
680 if (pd->info->status_mask == 0) in rockchip_pmu_domain_is_on()
683 regmap_read(pmu->regmap, pmu->info->status_offset, &val); in rockchip_pmu_domain_is_on()
686 return !(val & pd->info->status_mask); in rockchip_pmu_domain_is_on()
692 struct rockchip_pmu *pmu = pd->pmu; in rockchip_do_pmu_set_power_domain()
693 struct generic_pm_domain *genpd = &pd->genpd; in rockchip_do_pmu_set_power_domain()
698 if (pd->info->pwr_mask == 0) in rockchip_do_pmu_set_power_domain()
701 if (on && pd->info->mem_status_mask) in rockchip_do_pmu_set_power_domain()
704 if (pd->info->pwr_offset) in rockchip_do_pmu_set_power_domain()
705 pd_pwr_offset = pd->info->pwr_offset; in rockchip_do_pmu_set_power_domain()
707 if (pd->info->pwr_w_mask) in rockchip_do_pmu_set_power_domain()
708 regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset, in rockchip_do_pmu_set_power_domain()
709 on ? pd->info->pwr_w_mask : in rockchip_do_pmu_set_power_domain()
710 (pd->info->pwr_mask | pd->info->pwr_w_mask)); in rockchip_do_pmu_set_power_domain()
712 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset + in rockchip_do_pmu_set_power_domain()
713 pd_pwr_offset, pd->info->pwr_mask, in rockchip_do_pmu_set_power_domain()
714 on ? 0 : -1U); in rockchip_do_pmu_set_power_domain()
727 dev_err(pmu->dev, in rockchip_do_pmu_set_power_domain()
729 genpd->name, on, is_on); in rockchip_do_pmu_set_power_domain()
741 struct rockchip_pmu *pmu = pd->pmu; in rockchip_pd_power()
743 struct generic_pm_domain *genpd = &pd->genpd; in rockchip_pd_power()
749 if (genpd->name && !strcmp(genpd->name, "gpu")) in rockchip_pd_power()
756 if (IS_ERR_OR_NULL(pd->supply) && in rockchip_pd_power()
757 PTR_ERR(pd->supply) != -ENODEV) in rockchip_pd_power()
758 pd->supply = devm_regulator_get_optional(pd->pmu->dev, in rockchip_pd_power()
759 genpd->name); in rockchip_pd_power()
761 if (power_on && !IS_ERR(pd->supply)) { in rockchip_pd_power()
762 ret = regulator_enable(pd->supply); in rockchip_pd_power()
764 dev_err(pd->pmu->dev, "failed to set vdd supply enable '%s',\n", in rockchip_pd_power()
765 genpd->name); in rockchip_pd_power()
771 ret = clk_bulk_enable(pd->num_clks, pd->clks); in rockchip_pd_power()
773 dev_err(pmu->dev, "failed to enable clocks\n"); in rockchip_pd_power()
781 pd->is_qos_saved = true; in rockchip_pd_power()
786 dev_err(pd->pmu->dev, "failed to set idle request '%s',\n", in rockchip_pd_power()
787 genpd->name); in rockchip_pd_power()
795 dev_err(pd->pmu->dev, "failed to set power '%s' = %d,\n", in rockchip_pd_power()
796 genpd->name, power_on); in rockchip_pd_power()
805 dev_err(pd->pmu->dev, "failed to set deidle request '%s',\n", in rockchip_pd_power()
806 genpd->name); in rockchip_pd_power()
810 if (pd->is_qos_saved) in rockchip_pd_power()
812 if (pd->is_qos_need_init) in rockchip_pd_power()
818 clk_bulk_disable(pd->num_clks, pd->clks); in rockchip_pd_power()
820 if (!power_on && !IS_ERR(pd->supply)) in rockchip_pd_power()
821 ret = regulator_disable(pd->supply); in rockchip_pd_power()
832 if (pd->is_ignore_pwr) in rockchip_pd_power_on()
842 if (pd->is_ignore_pwr) in rockchip_pd_power_off()
854 return -EINVAL; in rockchip_pmu_pd_on()
856 if (IS_ERR_OR_NULL(dev->pm_domain)) in rockchip_pmu_pd_on()
857 return -EINVAL; in rockchip_pmu_pd_on()
859 genpd = pd_to_genpd(dev->pm_domain); in rockchip_pmu_pd_on()
872 return -EINVAL; in rockchip_pmu_pd_off()
874 if (IS_ERR_OR_NULL(dev->pm_domain)) in rockchip_pmu_pd_off()
875 return -EINVAL; in rockchip_pmu_pd_off()
877 genpd = pd_to_genpd(dev->pm_domain); in rockchip_pmu_pd_off()
893 if (IS_ERR_OR_NULL(dev->pm_domain)) in rockchip_pmu_pd_is_on()
896 genpd = pd_to_genpd(dev->pm_domain); in rockchip_pmu_pd_is_on()
914 dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name); in rockchip_pd_attach_dev()
923 while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) { in rockchip_pd_attach_dev()
940 dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name); in rockchip_pd_detach_dev()
949 if (!pd->is_qos_need_init) { in rockchip_pd_qos_init()
950 kfree(pd->qos_is_need_init[0]); in rockchip_pd_qos_init()
951 pd->qos_is_need_init[0] = NULL; in rockchip_pd_qos_init()
957 ret = clk_bulk_enable(pd->num_clks, pd->clks); in rockchip_pd_qos_init()
959 dev_err(pd->pmu->dev, "failed to enable clocks\n"); in rockchip_pd_qos_init()
963 clk_bulk_disable(pd->num_clks, pd->clks); in rockchip_pd_qos_init()
971 if (pd->genpd.flags & GENPD_FLAG_ALWAYS_ON) in rockchip_pd_add_alwasy_on_flag()
973 pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON; in rockchip_pd_add_alwasy_on_flag()
977 dev_err(pd->pmu->dev, in rockchip_pd_add_alwasy_on_flag()
979 pd->genpd.name, error); in rockchip_pd_add_alwasy_on_flag()
1000 dev_err(pmu->dev, in rockchip_pm_add_one_domain()
1003 return -EINVAL; in rockchip_pm_add_one_domain()
1006 if (id >= pmu->info->num_domains) { in rockchip_pm_add_one_domain()
1007 dev_err(pmu->dev, "%pOFn: invalid domain id %d\n", in rockchip_pm_add_one_domain()
1009 return -EINVAL; in rockchip_pm_add_one_domain()
1011 if (pmu->genpd_data.domains[id]) in rockchip_pm_add_one_domain()
1014 pd_info = &pmu->info->domain_info[id]; in rockchip_pm_add_one_domain()
1016 dev_err(pmu->dev, "%pOFn: undefined domain id %d\n", in rockchip_pm_add_one_domain()
1018 return -EINVAL; in rockchip_pm_add_one_domain()
1021 pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL); in rockchip_pm_add_one_domain()
1023 return -ENOMEM; in rockchip_pm_add_one_domain()
1025 pd->info = pd_info; in rockchip_pm_add_one_domain()
1026 pd->pmu = pmu; in rockchip_pm_add_one_domain()
1027 if (!pd_info->pwr_mask) in rockchip_pm_add_one_domain()
1028 pd->is_ignore_pwr = true; in rockchip_pm_add_one_domain()
1030 pd->num_clks = of_clk_get_parent_count(node); in rockchip_pm_add_one_domain()
1031 if (pd->num_clks > 0) { in rockchip_pm_add_one_domain()
1032 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks, in rockchip_pm_add_one_domain()
1033 sizeof(*pd->clks), GFP_KERNEL); in rockchip_pm_add_one_domain()
1034 if (!pd->clks) in rockchip_pm_add_one_domain()
1035 return -ENOMEM; in rockchip_pm_add_one_domain()
1037 dev_dbg(pmu->dev, "%pOFn: doesn't have clocks: %d\n", in rockchip_pm_add_one_domain()
1038 node, pd->num_clks); in rockchip_pm_add_one_domain()
1039 pd->num_clks = 0; in rockchip_pm_add_one_domain()
1042 for (i = 0; i < pd->num_clks; i++) { in rockchip_pm_add_one_domain()
1043 pd->clks[i].clk = of_clk_get(node, i); in rockchip_pm_add_one_domain()
1044 if (IS_ERR(pd->clks[i].clk)) { in rockchip_pm_add_one_domain()
1045 error = PTR_ERR(pd->clks[i].clk); in rockchip_pm_add_one_domain()
1046 dev_err(pmu->dev, in rockchip_pm_add_one_domain()
1053 error = clk_bulk_prepare(pd->num_clks, pd->clks); in rockchip_pm_add_one_domain()
1062 pd->num_qos++; in rockchip_pm_add_one_domain()
1066 if (pd->num_qos > 0) { in rockchip_pm_add_one_domain()
1067 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos, in rockchip_pm_add_one_domain()
1068 sizeof(*pd->qos_regmap), in rockchip_pm_add_one_domain()
1070 if (!pd->qos_regmap) { in rockchip_pm_add_one_domain()
1071 error = -ENOMEM; in rockchip_pm_add_one_domain()
1075 pd->qos_save_regs[0] = (u32 *)devm_kmalloc(pmu->dev, in rockchip_pm_add_one_domain()
1078 pd->num_qos, in rockchip_pm_add_one_domain()
1080 if (!pd->qos_save_regs[0]) { in rockchip_pm_add_one_domain()
1081 error = -ENOMEM; in rockchip_pm_add_one_domain()
1084 pd->qos_is_need_init[0] = kzalloc(sizeof(bool) * in rockchip_pm_add_one_domain()
1086 pd->num_qos, in rockchip_pm_add_one_domain()
1088 if (!pd->qos_is_need_init[0]) { in rockchip_pm_add_one_domain()
1089 error = -ENOMEM; in rockchip_pm_add_one_domain()
1093 pd->qos_save_regs[i] = pd->qos_save_regs[i - 1] + in rockchip_pm_add_one_domain()
1095 pd->qos_is_need_init[i] = pd->qos_is_need_init[i - 1] + in rockchip_pm_add_one_domain()
1102 error = -ENODEV; in rockchip_pm_add_one_domain()
1106 pd->qos_regmap[num_qos_reg] = in rockchip_pm_add_one_domain()
1108 if (IS_ERR(pd->qos_regmap[num_qos_reg])) { in rockchip_pm_add_one_domain()
1109 error = -ENODEV; in rockchip_pm_add_one_domain()
1114 "priority-init", in rockchip_pm_add_one_domain()
1116 pd->qos_save_regs[0][j] = val; in rockchip_pm_add_one_domain()
1117 pd->qos_is_need_init[0][j] = true; in rockchip_pm_add_one_domain()
1118 pd->is_qos_need_init = true; in rockchip_pm_add_one_domain()
1122 "mode-init", in rockchip_pm_add_one_domain()
1124 pd->qos_save_regs[1][j] = val; in rockchip_pm_add_one_domain()
1125 pd->qos_is_need_init[1][j] = true; in rockchip_pm_add_one_domain()
1126 pd->is_qos_need_init = true; in rockchip_pm_add_one_domain()
1130 "bandwidth-init", in rockchip_pm_add_one_domain()
1132 pd->qos_save_regs[2][j] = val; in rockchip_pm_add_one_domain()
1133 pd->qos_is_need_init[2][j] = true; in rockchip_pm_add_one_domain()
1134 pd->is_qos_need_init = true; in rockchip_pm_add_one_domain()
1138 "saturation-init", in rockchip_pm_add_one_domain()
1140 pd->qos_save_regs[3][j] = val; in rockchip_pm_add_one_domain()
1141 pd->qos_is_need_init[3][j] = true; in rockchip_pm_add_one_domain()
1142 pd->is_qos_need_init = true; in rockchip_pm_add_one_domain()
1146 "extcontrol-init", in rockchip_pm_add_one_domain()
1148 pd->qos_save_regs[4][j] = val; in rockchip_pm_add_one_domain()
1149 pd->qos_is_need_init[4][j] = true; in rockchip_pm_add_one_domain()
1150 pd->is_qos_need_init = true; in rockchip_pm_add_one_domain()
1156 if (num_qos_reg > pd->num_qos) { in rockchip_pm_add_one_domain()
1157 error = -EINVAL; in rockchip_pm_add_one_domain()
1163 if (pd->info->name) in rockchip_pm_add_one_domain()
1164 pd->genpd.name = pd->info->name; in rockchip_pm_add_one_domain()
1166 pd->genpd.name = kbasename(node->full_name); in rockchip_pm_add_one_domain()
1167 pd->genpd.power_off = rockchip_pd_power_off; in rockchip_pm_add_one_domain()
1168 pd->genpd.power_on = rockchip_pd_power_on; in rockchip_pm_add_one_domain()
1169 pd->genpd.attach_dev = rockchip_pd_attach_dev; in rockchip_pm_add_one_domain()
1170 pd->genpd.detach_dev = rockchip_pd_detach_dev; in rockchip_pm_add_one_domain()
1171 if (pd_info->active_wakeup) in rockchip_pm_add_one_domain()
1172 pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; in rockchip_pm_add_one_domain()
1173 if (pd_info->always_on || pd_info->keepon_startup) { in rockchip_pm_add_one_domain()
1180 pm_genpd_init(&pd->genpd, NULL, !rockchip_pmu_domain_is_on(pd)); in rockchip_pm_add_one_domain()
1182 pmu->genpd_data.domains[id] = &pd->genpd; in rockchip_pm_add_one_domain()
1186 kfree(pd->qos_is_need_init[0]); in rockchip_pm_add_one_domain()
1187 pd->qos_is_need_init[0] = NULL; in rockchip_pm_add_one_domain()
1188 clk_bulk_unprepare(pd->num_clks, pd->clks); in rockchip_pm_add_one_domain()
1190 clk_bulk_put(pd->num_clks, pd->clks); in rockchip_pm_add_one_domain()
1202 ret = pm_genpd_remove(&pd->genpd); in rockchip_pm_remove_one_domain()
1204 dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n", in rockchip_pm_remove_one_domain()
1205 pd->genpd.name, ret); in rockchip_pm_remove_one_domain()
1207 clk_bulk_unprepare(pd->num_clks, pd->clks); in rockchip_pm_remove_one_domain()
1208 clk_bulk_put(pd->num_clks, pd->clks); in rockchip_pm_remove_one_domain()
1210 /* protect the zeroing of pm->num_clks */ in rockchip_pm_remove_one_domain()
1212 pd->num_clks = 0; in rockchip_pm_remove_one_domain()
1224 for (i = 0; i < pmu->genpd_data.num_domains; i++) { in rockchip_pm_domain_cleanup()
1225 genpd = pmu->genpd_data.domains[i]; in rockchip_pm_domain_cleanup()
1240 regmap_write(pmu->regmap, domain_reg_offset, count); in rockchip_configure_pd_cnt()
1242 regmap_write(pmu->regmap, domain_reg_offset + 4, count); in rockchip_configure_pd_cnt()
1258 dev_err(pmu->dev, in rockchip_pm_add_subdomain()
1263 parent_domain = pmu->genpd_data.domains[idx]; in rockchip_pm_add_subdomain()
1267 dev_err(pmu->dev, "failed to handle node %pOFn: %d\n", in rockchip_pm_add_subdomain()
1274 dev_err(pmu->dev, in rockchip_pm_add_subdomain()
1279 child_domain = pmu->genpd_data.domains[idx]; in rockchip_pm_add_subdomain()
1283 dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n", in rockchip_pm_add_subdomain()
1284 parent_domain->name, child_domain->name, error); in rockchip_pm_add_subdomain()
1287 dev_dbg(pmu->dev, "%s add subdomain: %s\n", in rockchip_pm_add_subdomain()
1288 parent_domain->name, child_domain->name); in rockchip_pm_add_subdomain()
1299 if (!parent_pd->is_ignore_pwr) in rockchip_pm_add_subdomain()
1300 child_pd->is_ignore_pwr = false; in rockchip_pm_add_subdomain()
1321 for (i = 0; i < g_pmu->genpd_data.num_domains; i++) { in rockchip_pd_keepon_do_release()
1322 genpd = g_pmu->genpd_data.domains[i]; in rockchip_pd_keepon_do_release()
1325 if (pd->info->always_on) in rockchip_pd_keepon_do_release()
1327 if (!pd->info->keepon_startup) in rockchip_pd_keepon_do_release()
1329 if (!(genpd->flags & GENPD_FLAG_ALWAYS_ON)) in rockchip_pd_keepon_do_release()
1331 genpd->flags &= (~GENPD_FLAG_ALWAYS_ON); in rockchip_pd_keepon_do_release()
1332 queue_work(pm_wq, &genpd->power_off_work); in rockchip_pd_keepon_do_release()
1354 pr_warn("%-9s 0x%04x: ", name, offset); in dump_offset()
1364 dump_offset("pwr", g_pmu->info->pwr_offset); in rockchip_dump_pmu()
1365 dump_offset("status", g_pmu->info->status_offset); in rockchip_dump_pmu()
1366 dump_offset("req", g_pmu->info->req_offset); in rockchip_dump_pmu()
1367 dump_offset("idle", g_pmu->info->idle_offset); in rockchip_dump_pmu()
1368 dump_offset("ack", g_pmu->info->ack_offset); in rockchip_dump_pmu()
1369 dump_offset("mem_pwr", g_pmu->info->mem_pwr_offset); in rockchip_dump_pmu()
1370 dump_offset("chain_st", g_pmu->info->chain_status_offset); in rockchip_dump_pmu()
1371 dump_offset("mem_st", g_pmu->info->mem_status_offset); in rockchip_dump_pmu()
1372 dump_offset("repair_st", g_pmu->info->repair_status_offset); in rockchip_dump_pmu()
1373 dump_offset("clkungate", g_pmu->info->clk_ungate_offset); in rockchip_dump_pmu()
1374 dump_offset("mem_sd", g_pmu->info->mem_sd_offset); in rockchip_dump_pmu()
1391 struct device *dev = &pdev->dev; in rockchip_pm_domain_probe()
1392 struct device_node *np = dev->of_node; in rockchip_pm_domain_probe()
1403 return -ENODEV; in rockchip_pm_domain_probe()
1406 match = of_match_device(dev->driver->of_match_table, dev); in rockchip_pm_domain_probe()
1407 if (!match || !match->data) { in rockchip_pm_domain_probe()
1409 return -EINVAL; in rockchip_pm_domain_probe()
1412 pmu_info = match->data; in rockchip_pm_domain_probe()
1415 struct_size(pmu, domains, pmu_info->num_domains), in rockchip_pm_domain_probe()
1418 return -ENOMEM; in rockchip_pm_domain_probe()
1420 pmu->dev = &pdev->dev; in rockchip_pm_domain_probe()
1421 mutex_init(&pmu->mutex); in rockchip_pm_domain_probe()
1423 pmu->info = pmu_info; in rockchip_pm_domain_probe()
1425 pmu->genpd_data.domains = pmu->domains; in rockchip_pm_domain_probe()
1426 pmu->genpd_data.num_domains = pmu_info->num_domains; in rockchip_pm_domain_probe()
1428 parent = dev->parent; in rockchip_pm_domain_probe()
1431 return -ENODEV; in rockchip_pm_domain_probe()
1434 pmu->regmap = syscon_node_to_regmap(parent->of_node); in rockchip_pm_domain_probe()
1435 if (IS_ERR(pmu->regmap)) { in rockchip_pm_domain_probe()
1437 return PTR_ERR(pmu->regmap); in rockchip_pm_domain_probe()
1440 reg_base = of_iomap(parent->of_node, 0); in rockchip_pm_domain_probe()
1443 return -ENOMEM; in rockchip_pm_domain_probe()
1452 if (pmu_info->core_power_transition_time) in rockchip_pm_domain_probe()
1453 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset, in rockchip_pm_domain_probe()
1454 pmu_info->core_power_transition_time); in rockchip_pm_domain_probe()
1455 if (pmu_info->gpu_pwrcnt_offset) in rockchip_pm_domain_probe()
1456 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset, in rockchip_pm_domain_probe()
1457 pmu_info->gpu_power_transition_time); in rockchip_pm_domain_probe()
1459 error = -ENODEV; in rockchip_pm_domain_probe()
1484 error = of_genpd_add_provider_onecell(np, &pmu->genpd_data); in rockchip_pm_domain_probe()
1574 [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false),
1924 .compatible = "rockchip,px30-power-controller",
1928 .compatible = "rockchip,rk1808-power-controller",
1932 .compatible = "rockchip,rk3036-power-controller",
1936 .compatible = "rockchip,rk3066-power-controller",
1940 .compatible = "rockchip,rk3128-power-controller",
1944 .compatible = "rockchip,rk3188-power-controller",
1948 .compatible = "rockchip,rk3228-power-controller",
1952 .compatible = "rockchip,rk3288-power-controller",
1956 .compatible = "rockchip,rk3328-power-controller",
1960 .compatible = "rockchip,rk3366-power-controller",
1964 .compatible = "rockchip,rk3368-power-controller",
1968 .compatible = "rockchip,rk3399-power-controller",
1973 .compatible = "rockchip,rk3528-power-controller",
1978 .compatible = "rockchip,rk3562-power-controller",
1982 .compatible = "rockchip,rk3568-power-controller",
1986 .compatible = "rockchip,rk3588-power-controller",
1990 .compatible = "rockchip,rv1126-power-controller",
2000 .name = "rockchip-pm-domain",