40 	struct qe_gpio_chip *qe_gc =  in qe_gpio_save_regs()  local
44 	qe_gc->cpdata = qe_ioread32be(&regs->cpdata);  in qe_gpio_save_regs()
45 	qe_gc->saved_regs.cpdata = qe_gc->cpdata;  in qe_gpio_save_regs()
46 	qe_gc->saved_regs.cpdir1 = qe_ioread32be(&regs->cpdir1);  in qe_gpio_save_regs()
47 	qe_gc->saved_regs.cpdir2 = qe_ioread32be(&regs->cpdir2);  in qe_gpio_save_regs()
48 	qe_gc->saved_regs.cppar1 = qe_ioread32be(&regs->cppar1);  in qe_gpio_save_regs()
49 	qe_gc->saved_regs.cppar2 = qe_ioread32be(&regs->cppar2);  in qe_gpio_save_regs()
50 	qe_gc->saved_regs.cpodr = qe_ioread32be(&regs->cpodr);  in qe_gpio_save_regs()
65 	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);  in qe_gpio_set()  local
70 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_gpio_set()
73 		qe_gc->cpdata |= pin_mask;  in qe_gpio_set()
75 		qe_gc->cpdata &= ~pin_mask;  in qe_gpio_set()
77 	qe_iowrite32be(qe_gc->cpdata, &regs->cpdata);  in qe_gpio_set()
79 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_gpio_set()
86 	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);  in qe_gpio_set_multiple()  local
91 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_gpio_set_multiple()
98 				qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i));  in qe_gpio_set_multiple()
100 				qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i));  in qe_gpio_set_multiple()
104 	qe_iowrite32be(qe_gc->cpdata, &regs->cpdata);  in qe_gpio_set_multiple()
106 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_gpio_set_multiple()
112 	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);  in qe_gpio_dir_in()  local
115 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_gpio_dir_in()
119 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_gpio_dir_in()
127 	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);  in qe_gpio_dir_out()  local
132 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_gpio_dir_out()
136 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_gpio_dir_out()
163 	struct qe_gpio_chip *qe_gc;  in qe_pin_request()  local
188 	qe_gc = gpiochip_get_data(gc);  in qe_pin_request()
190 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_pin_request()
193 	if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {  in qe_pin_request()
194 		qe_pin->controller = qe_gc;  in qe_pin_request()
201 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_pin_request()
222 	struct qe_gpio_chip *qe_gc = qe_pin->controller;  in qe_pin_free()  local
226 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_pin_free()
227 	test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);  in qe_pin_free()
228 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_pin_free()
244 	struct qe_gpio_chip *qe_gc = qe_pin->controller;  in qe_pin_set_dedicated()  local
245 	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;  in qe_pin_set_dedicated()
246 	struct qe_pio_regs *sregs = &qe_gc->saved_regs;  in qe_pin_set_dedicated()
253 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_pin_set_dedicated()
268 		qe_gc->cpdata |= mask1;  in qe_pin_set_dedicated()
270 		qe_gc->cpdata &= ~mask1;  in qe_pin_set_dedicated()
272 	qe_iowrite32be(qe_gc->cpdata, &regs->cpdata);  in qe_pin_set_dedicated()
275 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_pin_set_dedicated()
288 	struct qe_gpio_chip *qe_gc = qe_pin->controller;  in qe_pin_set_gpio()  local
289 	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;  in qe_pin_set_gpio()
292 	spin_lock_irqsave(&qe_gc->lock, flags);  in qe_pin_set_gpio()
297 	spin_unlock_irqrestore(&qe_gc->lock, flags);  in qe_pin_set_gpio()
307 		struct qe_gpio_chip *qe_gc;  in qe_add_gpiochips()  local
311 		qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);  in qe_add_gpiochips()
312 		if (!qe_gc) {  in qe_add_gpiochips()
317 		spin_lock_init(&qe_gc->lock);  in qe_add_gpiochips()
319 		mm_gc = &qe_gc->mm_gc;  in qe_add_gpiochips()
330 		ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);  in qe_add_gpiochips()
337 		kfree(qe_gc);  in qe_add_gpiochips()