714 		ufshcd_writel(hba, (1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);  in ufshcd_utrl_clear()
716 		ufshcd_writel(hba, ~(1 << pos),  in ufshcd_utrl_clear()
728 		ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);  in ufshcd_utmrl_clear()
730 		ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);  in ufshcd_utmrl_clear()
838 	ufshcd_writel(hba, INT_AGGR_ENABLE |  in ufshcd_reset_intr_aggr()
852 	ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |  in ufshcd_config_intr_aggr()
864 	ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);  in ufshcd_disable_intr_aggr()
875 	ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,  in ufshcd_enable_run_stop_reg()
877 	ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,  in ufshcd_enable_run_stop_reg()
892 	ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);  in ufshcd_hba_start()
2105 		ufshcd_writel(hba, 1 << task_tag,  in ufshcd_send_command()
2112 		ufshcd_writel(hba, 1 << task_tag,  in ufshcd_send_command()
2245 	ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);  in ufshcd_dispatch_uic_cmd()
2246 	ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);  in ufshcd_dispatch_uic_cmd()
2247 	ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);  in ufshcd_dispatch_uic_cmd()
2252 	ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,  in ufshcd_dispatch_uic_cmd()
2421 	ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);  in ufshcd_enable_intr()
2443 	ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);  in ufshcd_disable_intr()
4167 	ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);  in ufshcd_auto_hibern8_enable()
4433 	ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),  in ufshcd_make_hba_operational()
4435 	ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),  in ufshcd_make_hba_operational()
4437 	ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),  in ufshcd_make_hba_operational()
4439 	ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),  in ufshcd_make_hba_operational()
4478 	ufshcd_writel(hba, CONTROLLER_DISABLE,  REG_CONTROLLER_ENABLE);  in ufshcd_hba_stop()
5259 			ufshcd_writel(hba, utrlcnr,  in ufshcd_trc_handler()
6439 			ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);  in ufshcd_intr()
6516 	ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL);  in __ufshcd_issue_tm_cmd()
9352 	ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),  in ufshcd_init()
9354 	ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);  in ufshcd_init()