169 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1);  in exynos7_ufs_pre_link()
171 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12));  in exynos7_ufs_pre_link()
172 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1);  in exynos7_ufs_pre_link()
173 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1);  in exynos7_ufs_pre_link()
174 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1);  in exynos7_ufs_pre_link()
176 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val);  in exynos7_ufs_pre_link()
196 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xbb8);  in exynos7_ufs_post_link()
216 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_RXPHY_CFGUPDT), 0x1);  in exynos7_ufs_post_pwr_change()
220 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 0x1);  in exynos7_ufs_post_pwr_change()
330 		UIC_ARG_MIB(CMN_PWM_CLK_CTRL), attr->cmn_pwm_clk_ctrl);  in exynos_ufs_set_pwm_clk_div()
356 		ufshcd_dme_get(hba, UIC_ARG_MIB(CMN_PWM_CLK_CTRL), &clk_idx);  in exynos_ufs_calc_pwm_clk_div()
542 	ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_IDLE);  in exynos_ufs_establish_connt()
545 	ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), DEV_ID);  in exynos_ufs_establish_connt()
546 	ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), TRUE);  in exynos_ufs_establish_connt()
547 	ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), PEER_DEV_ID);  in exynos_ufs_establish_connt()
548 	ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERCPORTID), PEER_CPORT_ID);  in exynos_ufs_establish_connt()
549 	ufshcd_dme_set(hba, UIC_ARG_MIB(T_CPORTFLAGS), CPORT_DEF_FLAGS);  in exynos_ufs_establish_connt()
550 	ufshcd_dme_set(hba, UIC_ARG_MIB(T_TRAFFICCLASS), TRAFFIC_CLASS);  in exynos_ufs_establish_connt()
551 	ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED);  in exynos_ufs_establish_connt()
657 	ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064);  in exynos_ufs_pre_pwr_mode()
658 	ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224);  in exynos_ufs_pre_pwr_mode()
659 	ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160);  in exynos_ufs_pre_pwr_mode()
751 		ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES),  in exynos_ufs_phy_init()
753 		ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES),  in exynos_ufs_phy_init()
780 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD),  in exynos_ufs_config_unipro()
782 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS),  in exynos_ufs_config_unipro()
784 	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE),  in exynos_ufs_config_unipro()
859 			UIC_ARG_MIB(T_DBG_SKIP_INIT_HIBERN8_EXIT), TRUE);  in exynos_ufs_post_link()
863 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_GRANULARITY),  in exynos_ufs_post_link()
868 			ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),  in exynos_ufs_post_link()
872 			ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),  in exynos_ufs_post_link()
878 			ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),  in exynos_ufs_post_link()
881 			ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME),  in exynos_ufs_post_link()
886 		ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 0);  in exynos_ufs_post_link()
1100 		ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &cur_mode);  in exynos_ufs_post_hibern8()