33 #define dma_write32(VAL, REG) \  macro
240 		dma_write32(val | DMA_RST_SCSI, DMA_CSR);  in sbus_esp_reset_dma()
241 		dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);  in sbus_esp_reset_dma()
245 		dma_write32(DMA_RESET_FAS366, DMA_CSR);  in sbus_esp_reset_dma()
246 		dma_write32(DMA_RST_SCSI, DMA_CSR);  in sbus_esp_reset_dma()
275 		dma_write32(0, DMA_CSR);  in sbus_esp_reset_dma()
276 		dma_write32(esp->prev_hme_dmacsr, DMA_CSR);  in sbus_esp_reset_dma()
278 		dma_write32(0, DMA_ADDR);  in sbus_esp_reset_dma()
284 			dma_write32(val | DMA_3CLKS, DMA_CSR);  in sbus_esp_reset_dma()
296 		dma_write32(val, DMA_CSR);  in sbus_esp_reset_dma()
308 		dma_write32(val, DMA_CSR);  in sbus_esp_reset_dma()
317 	dma_write32(val | DMA_INT_ENAB, DMA_CSR);  in sbus_esp_reset_dma()
333 		dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);  in sbus_esp_dma_drain()
349 		dma_write32(DMA_RST_SCSI, DMA_CSR);  in sbus_esp_dma_invalidate()
356 		dma_write32(0, DMA_CSR);  in sbus_esp_dma_invalidate()
357 		dma_write32(esp->prev_hme_dmacsr, DMA_CSR);  in sbus_esp_dma_invalidate()
362 		dma_write32(0, DMA_ADDR);  in sbus_esp_dma_invalidate()
379 		dma_write32(val, DMA_CSR);  in sbus_esp_dma_invalidate()
381 		dma_write32(val, DMA_CSR);  in sbus_esp_dma_invalidate()
408 		dma_write32(dma_count, DMA_COUNT);  in sbus_esp_send_dma_cmd()
409 		dma_write32(addr, DMA_ADDR);  in sbus_esp_send_dma_cmd()
410 		dma_write32(csr, DMA_CSR);  in sbus_esp_send_dma_cmd()
418 		dma_write32(csr, DMA_CSR);  in sbus_esp_send_dma_cmd()
421 			dma_write32(end - addr, DMA_COUNT);  in sbus_esp_send_dma_cmd()
423 		dma_write32(addr, DMA_ADDR);  in sbus_esp_send_dma_cmd()
500 		dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);  in esp_sbus_probe_one()
564 	dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);  in esp_sbus_remove()