Lines Matching refs:ha
15 uint32_t qla4_83xx_rd_reg(struct scsi_qla_host *ha, ulong addr) in qla4_83xx_rd_reg() argument
17 return readl((void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_rd_reg()
20 void qla4_83xx_wr_reg(struct scsi_qla_host *ha, ulong addr, uint32_t val) in qla4_83xx_wr_reg() argument
22 writel(val, (void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_wr_reg()
25 static int qla4_83xx_set_win_base(struct scsi_qla_host *ha, uint32_t addr) in qla4_83xx_set_win_base() argument
30 qla4_83xx_wr_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num), addr); in qla4_83xx_set_win_base()
31 val = qla4_83xx_rd_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num)); in qla4_83xx_set_win_base()
33 ql4_printk(KERN_ERR, ha, "%s: Failed to set register window : addr written 0x%x, read 0x%x!\n", in qla4_83xx_set_win_base()
41 int qla4_83xx_rd_reg_indirect(struct scsi_qla_host *ha, uint32_t addr, in qla4_83xx_rd_reg_indirect() argument
46 ret_val = qla4_83xx_set_win_base(ha, addr); in qla4_83xx_rd_reg_indirect()
49 *data = qla4_83xx_rd_reg(ha, QLA83XX_WILDCARD); in qla4_83xx_rd_reg_indirect()
52 ql4_printk(KERN_ERR, ha, "%s: failed read of addr 0x%x!\n", in qla4_83xx_rd_reg_indirect()
59 int qla4_83xx_wr_reg_indirect(struct scsi_qla_host *ha, uint32_t addr, in qla4_83xx_wr_reg_indirect() argument
64 ret_val = qla4_83xx_set_win_base(ha, addr); in qla4_83xx_wr_reg_indirect()
67 qla4_83xx_wr_reg(ha, QLA83XX_WILDCARD, data); in qla4_83xx_wr_reg_indirect()
69 ql4_printk(KERN_ERR, ha, "%s: failed wrt to addr 0x%x, data 0x%x\n", in qla4_83xx_wr_reg_indirect()
75 static int qla4_83xx_flash_lock(struct scsi_qla_host *ha) in qla4_83xx_flash_lock() argument
83 lock_status = qla4_83xx_rd_reg(ha, QLA83XX_FLASH_LOCK); in qla4_83xx_flash_lock()
88 lock_owner = qla4_83xx_rd_reg(ha, in qla4_83xx_flash_lock()
90 ql4_printk(KERN_ERR, ha, "%s: flash lock by func %d failed, held by func %d\n", in qla4_83xx_flash_lock()
91 __func__, ha->func_num, lock_owner); in qla4_83xx_flash_lock()
98 qla4_83xx_wr_reg(ha, QLA83XX_FLASH_LOCK_ID, ha->func_num); in qla4_83xx_flash_lock()
102 static void qla4_83xx_flash_unlock(struct scsi_qla_host *ha) in qla4_83xx_flash_unlock() argument
105 qla4_83xx_wr_reg(ha, QLA83XX_FLASH_LOCK_ID, 0xFF); in qla4_83xx_flash_unlock()
106 qla4_83xx_rd_reg(ha, QLA83XX_FLASH_UNLOCK); in qla4_83xx_flash_unlock()
109 int qla4_83xx_flash_read_u32(struct scsi_qla_host *ha, uint32_t flash_addr, in qla4_83xx_flash_read_u32() argument
117 ret_val = qla4_83xx_flash_lock(ha); in qla4_83xx_flash_read_u32()
122 ql4_printk(KERN_ERR, ha, "%s: Illegal addr = 0x%x\n", in qla4_83xx_flash_read_u32()
129 ret_val = qla4_83xx_wr_reg_indirect(ha, in qla4_83xx_flash_read_u32()
133 ql4_printk(KERN_ERR, ha, "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW\n!", in qla4_83xx_flash_read_u32()
138 ret_val = qla4_83xx_rd_reg_indirect(ha, in qla4_83xx_flash_read_u32()
142 ql4_printk(KERN_ERR, ha, "%s: failed to read addr 0x%x!\n", in qla4_83xx_flash_read_u32()
153 qla4_83xx_flash_unlock(ha); in qla4_83xx_flash_read_u32()
159 int qla4_83xx_lockless_flash_read_u32(struct scsi_qla_host *ha, in qla4_83xx_lockless_flash_read_u32() argument
172 ql4_printk(KERN_ERR, ha, "%s: Illegal addr = 0x%x\n", in qla4_83xx_lockless_flash_read_u32()
178 ret_val = qla4_83xx_wr_reg_indirect(ha, QLA83XX_FLASH_DIRECT_WINDOW, in qla4_83xx_lockless_flash_read_u32()
181 ql4_printk(KERN_ERR, ha, "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n", in qla4_83xx_lockless_flash_read_u32()
192 ret_val = qla4_83xx_rd_reg_indirect(ha, in qla4_83xx_lockless_flash_read_u32()
196 ql4_printk(KERN_ERR, ha, "%s: failed to read addr 0x%x!\n", in qla4_83xx_lockless_flash_read_u32()
208 ret_val = qla4_83xx_wr_reg_indirect(ha, in qla4_83xx_lockless_flash_read_u32()
212 ql4_printk(KERN_ERR, ha, "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n", in qla4_83xx_lockless_flash_read_u32()
222 ret_val = qla4_83xx_rd_reg_indirect(ha, in qla4_83xx_lockless_flash_read_u32()
226 ql4_printk(KERN_ERR, ha, "%s: failed to read addr 0x%x!\n", in qla4_83xx_lockless_flash_read_u32()
241 void qla4_83xx_rom_lock_recovery(struct scsi_qla_host *ha) in qla4_83xx_rom_lock_recovery() argument
243 if (qla4_83xx_flash_lock(ha)) in qla4_83xx_rom_lock_recovery()
244 ql4_printk(KERN_INFO, ha, "%s: Resetting rom lock\n", __func__); in qla4_83xx_rom_lock_recovery()
250 qla4_83xx_flash_unlock(ha); in qla4_83xx_rom_lock_recovery()
256 static int qla4_83xx_lock_recovery(struct scsi_qla_host *ha) in qla4_83xx_lock_recovery() argument
262 lockid = ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY); in qla4_83xx_lock_recovery()
269 ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY, in qla4_83xx_lock_recovery()
270 (ha->func_num << 2) | INTENT_TO_RECOVER); in qla4_83xx_lock_recovery()
275 lockid = ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY); in qla4_83xx_lock_recovery()
276 if ((lockid & 0x3C) != (ha->func_num << 2)) in qla4_83xx_lock_recovery()
279 ql4_printk(KERN_INFO, ha, "%s: IDC Lock recovery initiated for func %d\n", in qla4_83xx_lock_recovery()
280 __func__, ha->func_num); in qla4_83xx_lock_recovery()
283 ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY, in qla4_83xx_lock_recovery()
284 (ha->func_num << 2) | PROCEED_TO_RECOVER); in qla4_83xx_lock_recovery()
287 ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCK_ID, 0xFF); in qla4_83xx_lock_recovery()
288 ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_UNLOCK); in qla4_83xx_lock_recovery()
291 ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY, 0); in qla4_83xx_lock_recovery()
294 lock = ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_LOCK); in qla4_83xx_lock_recovery()
296 lockid = ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_LOCK_ID); in qla4_83xx_lock_recovery()
297 lockid = ((lockid + (1 << 8)) & ~0xFF) | ha->func_num; in qla4_83xx_lock_recovery()
298 ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCK_ID, lockid); in qla4_83xx_lock_recovery()
308 int qla4_83xx_drv_lock(struct scsi_qla_host *ha) in qla4_83xx_drv_lock() argument
320 status = qla4_83xx_rd_reg(ha, QLA83XX_DRV_LOCK); in qla4_83xx_drv_lock()
324 lock_id = qla4_83xx_rd_reg(ha, QLA83XX_DRV_LOCK_ID); in qla4_83xx_drv_lock()
325 lock_id = ((lock_id + (1 << 8)) & ~0xFF) | ha->func_num; in qla4_83xx_drv_lock()
326 qla4_83xx_wr_reg(ha, QLA83XX_DRV_LOCK_ID, lock_id); in qla4_83xx_drv_lock()
333 first_owner = ha->isp_ops->rd_reg_direct(ha, in qla4_83xx_drv_lock()
338 tmo_owner = qla4_83xx_rd_reg(ha, QLA83XX_DRV_LOCK_ID); in qla4_83xx_drv_lock()
341 …ql4_printk(KERN_INFO, ha, "%s: Lock by func %d failed after 2s, lock held by func %d, lock count %… in qla4_83xx_drv_lock()
342 __func__, ha->func_num, func_num, lock_cnt, in qla4_83xx_drv_lock()
350 ql4_printk(KERN_INFO, ha, "%s: IDC lock failed for func %d\n", in qla4_83xx_drv_lock()
351 __func__, ha->func_num); in qla4_83xx_drv_lock()
356 ret_val = qla4_83xx_lock_recovery(ha); in qla4_83xx_drv_lock()
359 ql4_printk(KERN_INFO, ha, "%s: IDC lock Recovery by %d successful\n", in qla4_83xx_drv_lock()
360 __func__, ha->func_num); in qla4_83xx_drv_lock()
365 ql4_printk(KERN_INFO, ha, "%s: IDC lock Recovery by %d failed, Retrying timeout\n", in qla4_83xx_drv_lock()
366 __func__, ha->func_num); in qla4_83xx_drv_lock()
376 void qla4_83xx_drv_unlock(struct scsi_qla_host *ha) in qla4_83xx_drv_unlock() argument
380 id = qla4_83xx_rd_reg(ha, QLA83XX_DRV_LOCK_ID); in qla4_83xx_drv_unlock()
382 if ((id & 0xFF) != ha->func_num) { in qla4_83xx_drv_unlock()
383 ql4_printk(KERN_ERR, ha, "%s: IDC Unlock by %d failed, lock owner is %d\n", in qla4_83xx_drv_unlock()
384 __func__, ha->func_num, (id & 0xFF)); in qla4_83xx_drv_unlock()
389 qla4_83xx_wr_reg(ha, QLA83XX_DRV_LOCK_ID, (id | 0xFF)); in qla4_83xx_drv_unlock()
390 qla4_83xx_rd_reg(ha, QLA83XX_DRV_UNLOCK); in qla4_83xx_drv_unlock()
393 void qla4_83xx_set_idc_dontreset(struct scsi_qla_host *ha) in qla4_83xx_set_idc_dontreset() argument
397 idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL); in qla4_83xx_set_idc_dontreset()
399 qla4_83xx_wr_reg(ha, QLA83XX_IDC_DRV_CTRL, idc_ctrl); in qla4_83xx_set_idc_dontreset()
400 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: idc_ctrl = %d\n", __func__, in qla4_83xx_set_idc_dontreset()
404 void qla4_83xx_clear_idc_dontreset(struct scsi_qla_host *ha) in qla4_83xx_clear_idc_dontreset() argument
408 idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL); in qla4_83xx_clear_idc_dontreset()
410 qla4_83xx_wr_reg(ha, QLA83XX_IDC_DRV_CTRL, idc_ctrl); in qla4_83xx_clear_idc_dontreset()
411 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: idc_ctrl = %d\n", __func__, in qla4_83xx_clear_idc_dontreset()
415 int qla4_83xx_idc_dontreset(struct scsi_qla_host *ha) in qla4_83xx_idc_dontreset() argument
419 idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL); in qla4_83xx_idc_dontreset()
438 int qla4_83xx_can_perform_reset(struct scsi_qla_host *ha) in qla4_83xx_can_perform_reset() argument
452 dev_part1 = qla4_83xx_rd_reg(ha, in qla4_83xx_can_perform_reset()
453 ha->reg_tbl[QLA8XXX_CRB_DEV_PART_INFO]); in qla4_83xx_can_perform_reset()
454 dev_part2 = qla4_83xx_rd_reg(ha, QLA83XX_CRB_DEV_PART_INFO2); in qla4_83xx_can_perform_reset()
455 drv_active = qla4_83xx_rd_reg(ha, ha->reg_tbl[QLA8XXX_CRB_DRV_ACTIVE]); in qla4_83xx_can_perform_reset()
493 if (!nic_present && (ha->func_num == iscsi_func_low)) { in qla4_83xx_can_perform_reset()
494 DEBUG2(ql4_printk(KERN_INFO, ha, in qla4_83xx_can_perform_reset()
496 __func__, ha->func_num)); in qla4_83xx_can_perform_reset()
509 void qla4_83xx_need_reset_handler(struct scsi_qla_host *ha) in qla4_83xx_need_reset_handler() argument
514 ql4_printk(KERN_INFO, ha, "%s: Performing ISP error recovery\n", in qla4_83xx_need_reset_handler()
517 if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) { in qla4_83xx_need_reset_handler()
518 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: reset acknowledged\n", in qla4_83xx_need_reset_handler()
520 qla4_8xxx_set_rst_ready(ha); in qla4_83xx_need_reset_handler()
524 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); in qla4_83xx_need_reset_handler()
528 ql4_printk(KERN_INFO, ha, "%s: Non Reset owner dev init timeout\n", in qla4_83xx_need_reset_handler()
533 ha->isp_ops->idc_unlock(ha); in qla4_83xx_need_reset_handler()
535 ha->isp_ops->idc_lock(ha); in qla4_83xx_need_reset_handler()
537 dev_state = qla4_8xxx_rd_direct(ha, in qla4_83xx_need_reset_handler()
541 qla4_8xxx_set_rst_ready(ha); in qla4_83xx_need_reset_handler()
542 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); in qla4_83xx_need_reset_handler()
543 drv_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_STATE); in qla4_83xx_need_reset_handler()
544 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); in qla4_83xx_need_reset_handler()
546 ql4_printk(KERN_INFO, ha, "%s: drv_state = 0x%x, drv_active = 0x%x\n", in qla4_83xx_need_reset_handler()
551 ql4_printk(KERN_INFO, ha, "%s: %s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n", in qla4_83xx_need_reset_handler()
557 ha->isp_ops->idc_unlock(ha); in qla4_83xx_need_reset_handler()
559 ha->isp_ops->idc_lock(ha); in qla4_83xx_need_reset_handler()
561 drv_state = qla4_8xxx_rd_direct(ha, in qla4_83xx_need_reset_handler()
563 drv_active = qla4_8xxx_rd_direct(ha, in qla4_83xx_need_reset_handler()
568 ql4_printk(KERN_INFO, ha, "%s: Reset_owner turning off drv_active of non-acking function 0x%x\n", in qla4_83xx_need_reset_handler()
571 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DRV_ACTIVE, in qla4_83xx_need_reset_handler()
575 clear_bit(AF_8XXX_RST_OWNER, &ha->flags); in qla4_83xx_need_reset_handler()
577 qla4_8xxx_device_bootstrap(ha); in qla4_83xx_need_reset_handler()
581 void qla4_83xx_get_idc_param(struct scsi_qla_host *ha) in qla4_83xx_get_idc_param() argument
585 ret_val = qla4_83xx_flash_read_u32(ha, QLA83XX_IDC_PARAM_ADDR, in qla4_83xx_get_idc_param()
588 ha->nx_dev_init_timeout = idc_params & 0xFFFF; in qla4_83xx_get_idc_param()
589 ha->nx_reset_timeout = (idc_params >> 16) & 0xFFFF; in qla4_83xx_get_idc_param()
591 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT; in qla4_83xx_get_idc_param()
592 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT; in qla4_83xx_get_idc_param()
595 DEBUG2(ql4_printk(KERN_DEBUG, ha, in qla4_83xx_get_idc_param()
597 __func__, ha->nx_dev_init_timeout, in qla4_83xx_get_idc_param()
598 ha->nx_reset_timeout)); in qla4_83xx_get_idc_param()
603 static void qla4_83xx_dump_reset_seq_hdr(struct scsi_qla_host *ha) in qla4_83xx_dump_reset_seq_hdr() argument
607 if (!ha->reset_tmplt.buff) { in qla4_83xx_dump_reset_seq_hdr()
608 ql4_printk(KERN_ERR, ha, "%s: Error: Invalid reset_seq_template\n", in qla4_83xx_dump_reset_seq_hdr()
613 phdr = ha->reset_tmplt.buff; in qla4_83xx_dump_reset_seq_hdr()
615 DEBUG2(ql4_printk(KERN_INFO, ha, in qla4_83xx_dump_reset_seq_hdr()
623 static int qla4_83xx_copy_bootloader(struct scsi_qla_host *ha) in qla4_83xx_copy_bootloader() argument
631 dest = qla4_83xx_rd_reg(ha, QLA83XX_BOOTLOADER_ADDR); in qla4_83xx_copy_bootloader()
632 size = qla4_83xx_rd_reg(ha, QLA83XX_BOOTLOADER_SIZE); in qla4_83xx_copy_bootloader()
643 ql4_printk(KERN_ERR, ha, "%s: Failed to allocate memory for boot loader cache\n", in qla4_83xx_copy_bootloader()
649 ret_val = qla4_83xx_lockless_flash_read_u32(ha, src, p_cache, in qla4_83xx_copy_bootloader()
652 ql4_printk(KERN_ERR, ha, "%s: Error reading firmware from flash\n", in qla4_83xx_copy_bootloader()
656 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: Read firmware from flash\n", in qla4_83xx_copy_bootloader()
660 ret_val = qla4_8xxx_ms_mem_write_128b(ha, dest, (uint32_t *)p_cache, in qla4_83xx_copy_bootloader()
663 ql4_printk(KERN_ERR, ha, "%s: Error writing firmware to MS\n", in qla4_83xx_copy_bootloader()
668 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: Wrote firmware size %d to MS\n", in qla4_83xx_copy_bootloader()
678 static int qla4_83xx_check_cmd_peg_status(struct scsi_qla_host *ha) in qla4_83xx_check_cmd_peg_status() argument
684 val = qla4_83xx_rd_reg(ha, QLA83XX_CMDPEG_STATE); in qla4_83xx_check_cmd_peg_status()
686 DEBUG2(ql4_printk(KERN_INFO, ha, in qla4_83xx_check_cmd_peg_status()
708 static int qla4_83xx_poll_reg(struct scsi_qla_host *ha, uint32_t addr, in qla4_83xx_poll_reg() argument
716 ret_val = qla4_83xx_rd_reg_indirect(ha, addr, &value); in qla4_83xx_poll_reg()
724 ret_val = qla4_83xx_rd_reg_indirect(ha, addr, &value); in qla4_83xx_poll_reg()
737 ha->reset_tmplt.seq_error++; in qla4_83xx_poll_reg()
738 ql4_printk(KERN_ERR, ha, "%s: Poll Failed: 0x%08x 0x%08x 0x%08x\n", in qla4_83xx_poll_reg()
745 static int qla4_83xx_reset_seq_checksum_test(struct scsi_qla_host *ha) in qla4_83xx_reset_seq_checksum_test() argument
748 uint16_t *buff = (uint16_t *)ha->reset_tmplt.buff; in qla4_83xx_reset_seq_checksum_test()
749 int u16_count = ha->reset_tmplt.hdr->size / sizeof(uint16_t); in qla4_83xx_reset_seq_checksum_test()
762 ql4_printk(KERN_ERR, ha, "%s: Reset seq checksum failed\n", in qla4_83xx_reset_seq_checksum_test()
774 void qla4_83xx_read_reset_template(struct scsi_qla_host *ha) in qla4_83xx_read_reset_template() argument
780 ha->reset_tmplt.seq_error = 0; in qla4_83xx_read_reset_template()
781 ha->reset_tmplt.buff = vmalloc(QLA83XX_RESTART_TEMPLATE_SIZE); in qla4_83xx_read_reset_template()
782 if (ha->reset_tmplt.buff == NULL) { in qla4_83xx_read_reset_template()
783 ql4_printk(KERN_ERR, ha, "%s: Failed to allocate reset template resources\n", in qla4_83xx_read_reset_template()
788 p_buff = ha->reset_tmplt.buff; in qla4_83xx_read_reset_template()
794 DEBUG2(ql4_printk(KERN_INFO, ha, in qla4_83xx_read_reset_template()
799 ret_val = qla4_83xx_flash_read_u32(ha, addr, p_buff, in qla4_83xx_read_reset_template()
802 ql4_printk(KERN_ERR, ha, "%s: Failed to read reset template\n", in qla4_83xx_read_reset_template()
807 ha->reset_tmplt.hdr = in qla4_83xx_read_reset_template()
808 (struct qla4_83xx_reset_template_hdr *)ha->reset_tmplt.buff; in qla4_83xx_read_reset_template()
811 tmplt_hdr_size = ha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t); in qla4_83xx_read_reset_template()
813 (ha->reset_tmplt.hdr->signature != RESET_TMPLT_HDR_SIGNATURE)) { in qla4_83xx_read_reset_template()
814 ql4_printk(KERN_ERR, ha, "%s: Template Header size %d is invalid, tmplt_hdr_def_size %d\n", in qla4_83xx_read_reset_template()
819 addr = QLA83XX_RESET_TEMPLATE_ADDR + ha->reset_tmplt.hdr->hdr_size; in qla4_83xx_read_reset_template()
820 p_buff = ha->reset_tmplt.buff + ha->reset_tmplt.hdr->hdr_size; in qla4_83xx_read_reset_template()
821 tmplt_hdr_def_size = (ha->reset_tmplt.hdr->size - in qla4_83xx_read_reset_template()
822 ha->reset_tmplt.hdr->hdr_size) / sizeof(uint32_t); in qla4_83xx_read_reset_template()
824 DEBUG2(ql4_printk(KERN_INFO, ha, in qla4_83xx_read_reset_template()
826 __func__, ha->reset_tmplt.hdr->size)); in qla4_83xx_read_reset_template()
829 ret_val = qla4_83xx_flash_read_u32(ha, addr, p_buff, in qla4_83xx_read_reset_template()
832 ql4_printk(KERN_ERR, ha, "%s: Failed to read reset template\n", in qla4_83xx_read_reset_template()
838 if (qla4_83xx_reset_seq_checksum_test(ha)) { in qla4_83xx_read_reset_template()
839 ql4_printk(KERN_ERR, ha, "%s: Reset Seq checksum failed!\n", in qla4_83xx_read_reset_template()
843 DEBUG2(ql4_printk(KERN_INFO, ha, in qla4_83xx_read_reset_template()
848 ha->reset_tmplt.init_offset = ha->reset_tmplt.buff + in qla4_83xx_read_reset_template()
849 ha->reset_tmplt.hdr->init_seq_offset; in qla4_83xx_read_reset_template()
850 ha->reset_tmplt.start_offset = ha->reset_tmplt.buff + in qla4_83xx_read_reset_template()
851 ha->reset_tmplt.hdr->start_seq_offset; in qla4_83xx_read_reset_template()
852 ha->reset_tmplt.stop_offset = ha->reset_tmplt.buff + in qla4_83xx_read_reset_template()
853 ha->reset_tmplt.hdr->hdr_size; in qla4_83xx_read_reset_template()
854 qla4_83xx_dump_reset_seq_hdr(ha); in qla4_83xx_read_reset_template()
859 vfree(ha->reset_tmplt.buff); in qla4_83xx_read_reset_template()
872 static void qla4_83xx_read_write_crb_reg(struct scsi_qla_host *ha, in qla4_83xx_read_write_crb_reg() argument
877 qla4_83xx_rd_reg_indirect(ha, raddr, &value); in qla4_83xx_read_write_crb_reg()
878 qla4_83xx_wr_reg_indirect(ha, waddr, value); in qla4_83xx_read_write_crb_reg()
892 static void qla4_83xx_rmw_crb_reg(struct scsi_qla_host *ha, uint32_t raddr, in qla4_83xx_rmw_crb_reg() argument
899 value = ha->reset_tmplt.array[p_rmw_hdr->index_a]; in qla4_83xx_rmw_crb_reg()
901 qla4_83xx_rd_reg_indirect(ha, raddr, &value); in qla4_83xx_rmw_crb_reg()
909 qla4_83xx_wr_reg_indirect(ha, waddr, value); in qla4_83xx_rmw_crb_reg()
914 static void qla4_83xx_write_list(struct scsi_qla_host *ha, in qla4_83xx_write_list() argument
924 qla4_83xx_wr_reg_indirect(ha, p_entry->arg1, p_entry->arg2); in qla4_83xx_write_list()
930 static void qla4_83xx_read_write_list(struct scsi_qla_host *ha, in qla4_83xx_read_write_list() argument
940 qla4_83xx_read_write_crb_reg(ha, p_entry->arg1, p_entry->arg2); in qla4_83xx_read_write_list()
946 static void qla4_83xx_poll_list(struct scsi_qla_host *ha, in qla4_83xx_poll_list() argument
966 qla4_83xx_poll_reg(ha, p_entry->arg1, delay, in qla4_83xx_poll_list()
972 if (qla4_83xx_poll_reg(ha, p_entry->arg1, delay, in qla4_83xx_poll_list()
975 qla4_83xx_rd_reg_indirect(ha, p_entry->arg1, in qla4_83xx_poll_list()
977 qla4_83xx_rd_reg_indirect(ha, p_entry->arg2, in qla4_83xx_poll_list()
984 static void qla4_83xx_poll_write_list(struct scsi_qla_host *ha, in qla4_83xx_poll_write_list() argument
999 qla4_83xx_wr_reg_indirect(ha, p_entry->dr_addr, in qla4_83xx_poll_write_list()
1001 qla4_83xx_wr_reg_indirect(ha, p_entry->ar_addr, in qla4_83xx_poll_write_list()
1004 if (qla4_83xx_poll_reg(ha, p_entry->ar_addr, delay, in qla4_83xx_poll_write_list()
1007 DEBUG2(ql4_printk(KERN_INFO, ha, in qla4_83xx_poll_write_list()
1010 ha->reset_tmplt.seq_index)); in qla4_83xx_poll_write_list()
1016 static void qla4_83xx_read_modify_write(struct scsi_qla_host *ha, in qla4_83xx_read_modify_write() argument
1029 qla4_83xx_rmw_crb_reg(ha, p_entry->arg1, p_entry->arg2, in qla4_83xx_read_modify_write()
1036 static void qla4_83xx_pause(struct scsi_qla_host *ha, in qla4_83xx_pause() argument
1043 static void qla4_83xx_poll_read_list(struct scsi_qla_host *ha, in qla4_83xx_poll_read_list() argument
1060 qla4_83xx_wr_reg_indirect(ha, p_entry->ar_addr, in qla4_83xx_poll_read_list()
1063 if (qla4_83xx_poll_reg(ha, p_entry->ar_addr, delay, in qla4_83xx_poll_read_list()
1066 DEBUG2(ql4_printk(KERN_INFO, ha, in qla4_83xx_poll_read_list()
1069 ha->reset_tmplt.seq_index)); in qla4_83xx_poll_read_list()
1071 index = ha->reset_tmplt.array_index; in qla4_83xx_poll_read_list()
1072 qla4_83xx_rd_reg_indirect(ha, p_entry->dr_addr, in qla4_83xx_poll_read_list()
1074 ha->reset_tmplt.array[index++] = value; in qla4_83xx_poll_read_list()
1077 ha->reset_tmplt.array_index = 1; in qla4_83xx_poll_read_list()
1083 static void qla4_83xx_seq_end(struct scsi_qla_host *ha, in qla4_83xx_seq_end() argument
1086 ha->reset_tmplt.seq_end = 1; in qla4_83xx_seq_end()
1089 static void qla4_83xx_template_end(struct scsi_qla_host *ha, in qla4_83xx_template_end() argument
1092 ha->reset_tmplt.template_end = 1; in qla4_83xx_template_end()
1094 if (ha->reset_tmplt.seq_error == 0) { in qla4_83xx_template_end()
1095 DEBUG2(ql4_printk(KERN_INFO, ha, in qla4_83xx_template_end()
1099 ql4_printk(KERN_ERR, ha, "%s: Reset sequence completed with some timeout errors.\n", in qla4_83xx_template_end()
1115 static void qla4_83xx_process_reset_template(struct scsi_qla_host *ha, in qla4_83xx_process_reset_template() argument
1122 ha->reset_tmplt.seq_end = 0; in qla4_83xx_process_reset_template()
1123 ha->reset_tmplt.template_end = 0; in qla4_83xx_process_reset_template()
1124 entries = ha->reset_tmplt.hdr->entries; in qla4_83xx_process_reset_template()
1125 index = ha->reset_tmplt.seq_index; in qla4_83xx_process_reset_template()
1127 for (; (!ha->reset_tmplt.seq_end) && (index < entries); index++) { in qla4_83xx_process_reset_template()
1134 qla4_83xx_write_list(ha, p_hdr); in qla4_83xx_process_reset_template()
1137 qla4_83xx_read_write_list(ha, p_hdr); in qla4_83xx_process_reset_template()
1140 qla4_83xx_poll_list(ha, p_hdr); in qla4_83xx_process_reset_template()
1143 qla4_83xx_poll_write_list(ha, p_hdr); in qla4_83xx_process_reset_template()
1146 qla4_83xx_read_modify_write(ha, p_hdr); in qla4_83xx_process_reset_template()
1149 qla4_83xx_pause(ha, p_hdr); in qla4_83xx_process_reset_template()
1152 qla4_83xx_seq_end(ha, p_hdr); in qla4_83xx_process_reset_template()
1155 qla4_83xx_template_end(ha, p_hdr); in qla4_83xx_process_reset_template()
1158 qla4_83xx_poll_read_list(ha, p_hdr); in qla4_83xx_process_reset_template()
1161 ql4_printk(KERN_ERR, ha, "%s: Unknown command ==> 0x%04x on entry = %d\n", in qla4_83xx_process_reset_template()
1170 ha->reset_tmplt.seq_index = index; in qla4_83xx_process_reset_template()
1173 static void qla4_83xx_process_stop_seq(struct scsi_qla_host *ha) in qla4_83xx_process_stop_seq() argument
1175 ha->reset_tmplt.seq_index = 0; in qla4_83xx_process_stop_seq()
1176 qla4_83xx_process_reset_template(ha, ha->reset_tmplt.stop_offset); in qla4_83xx_process_stop_seq()
1178 if (ha->reset_tmplt.seq_end != 1) in qla4_83xx_process_stop_seq()
1179 ql4_printk(KERN_ERR, ha, "%s: Abrupt STOP Sub-Sequence end.\n", in qla4_83xx_process_stop_seq()
1183 static void qla4_83xx_process_start_seq(struct scsi_qla_host *ha) in qla4_83xx_process_start_seq() argument
1185 qla4_83xx_process_reset_template(ha, ha->reset_tmplt.start_offset); in qla4_83xx_process_start_seq()
1187 if (ha->reset_tmplt.template_end != 1) in qla4_83xx_process_start_seq()
1188 ql4_printk(KERN_ERR, ha, "%s: Abrupt START Sub-Sequence end.\n", in qla4_83xx_process_start_seq()
1192 static void qla4_83xx_process_init_seq(struct scsi_qla_host *ha) in qla4_83xx_process_init_seq() argument
1194 qla4_83xx_process_reset_template(ha, ha->reset_tmplt.init_offset); in qla4_83xx_process_init_seq()
1196 if (ha->reset_tmplt.seq_end != 1) in qla4_83xx_process_init_seq()
1197 ql4_printk(KERN_ERR, ha, "%s: Abrupt INIT Sub-Sequence end.\n", in qla4_83xx_process_init_seq()
1201 static int qla4_83xx_restart(struct scsi_qla_host *ha) in qla4_83xx_restart() argument
1206 qla4_83xx_process_stop_seq(ha); in qla4_83xx_restart()
1213 idc_ctrl = qla4_83xx_rd_reg(ha, QLA83XX_IDC_DRV_CTRL); in qla4_83xx_restart()
1215 qla4_83xx_wr_reg(ha, QLA83XX_IDC_DRV_CTRL, in qla4_83xx_restart()
1217 ql4_printk(KERN_INFO, ha, "%s: Graceful RESET: Not collecting minidump\n", in qla4_83xx_restart()
1220 qla4_8xxx_get_minidump(ha); in qla4_83xx_restart()
1223 qla4_83xx_process_init_seq(ha); in qla4_83xx_restart()
1225 if (qla4_83xx_copy_bootloader(ha)) { in qla4_83xx_restart()
1226 ql4_printk(KERN_ERR, ha, "%s: Copy bootloader, firmware restart failed!\n", in qla4_83xx_restart()
1232 qla4_83xx_wr_reg(ha, QLA83XX_FW_IMAGE_VALID, QLA83XX_BOOT_FROM_FLASH); in qla4_83xx_restart()
1233 qla4_83xx_process_start_seq(ha); in qla4_83xx_restart()
1239 int qla4_83xx_start_firmware(struct scsi_qla_host *ha) in qla4_83xx_start_firmware() argument
1243 ret_val = qla4_83xx_restart(ha); in qla4_83xx_start_firmware()
1245 ql4_printk(KERN_ERR, ha, "%s: Restart error\n", __func__); in qla4_83xx_start_firmware()
1248 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: Restart done\n", in qla4_83xx_start_firmware()
1252 ret_val = qla4_83xx_check_cmd_peg_status(ha); in qla4_83xx_start_firmware()
1254 ql4_printk(KERN_ERR, ha, "%s: Peg not initialized\n", in qla4_83xx_start_firmware()
1263 static void qla4_83xx_disable_iocb_intrs(struct scsi_qla_host *ha) in qla4_83xx_disable_iocb_intrs() argument
1265 if (test_and_clear_bit(AF_83XX_IOCB_INTR_ON, &ha->flags)) in qla4_83xx_disable_iocb_intrs()
1266 qla4_8xxx_intr_disable(ha); in qla4_83xx_disable_iocb_intrs()
1269 static void qla4_83xx_disable_mbox_intrs(struct scsi_qla_host *ha) in qla4_83xx_disable_mbox_intrs() argument
1273 if (test_and_clear_bit(AF_83XX_MBOX_INTR_ON, &ha->flags)) { in qla4_83xx_disable_mbox_intrs()
1274 ret = readl(&ha->qla4_83xx_reg->mbox_int); in qla4_83xx_disable_mbox_intrs()
1276 writel(mb_int, &ha->qla4_83xx_reg->mbox_int); in qla4_83xx_disable_mbox_intrs()
1277 writel(1, &ha->qla4_83xx_reg->leg_int_mask); in qla4_83xx_disable_mbox_intrs()
1281 void qla4_83xx_disable_intrs(struct scsi_qla_host *ha) in qla4_83xx_disable_intrs() argument
1283 qla4_83xx_disable_mbox_intrs(ha); in qla4_83xx_disable_intrs()
1284 qla4_83xx_disable_iocb_intrs(ha); in qla4_83xx_disable_intrs()
1287 static void qla4_83xx_enable_iocb_intrs(struct scsi_qla_host *ha) in qla4_83xx_enable_iocb_intrs() argument
1289 if (!test_bit(AF_83XX_IOCB_INTR_ON, &ha->flags)) { in qla4_83xx_enable_iocb_intrs()
1290 qla4_8xxx_intr_enable(ha); in qla4_83xx_enable_iocb_intrs()
1291 set_bit(AF_83XX_IOCB_INTR_ON, &ha->flags); in qla4_83xx_enable_iocb_intrs()
1295 void qla4_83xx_enable_mbox_intrs(struct scsi_qla_host *ha) in qla4_83xx_enable_mbox_intrs() argument
1299 if (!test_bit(AF_83XX_MBOX_INTR_ON, &ha->flags)) { in qla4_83xx_enable_mbox_intrs()
1301 writel(mb_int, &ha->qla4_83xx_reg->mbox_int); in qla4_83xx_enable_mbox_intrs()
1302 writel(0, &ha->qla4_83xx_reg->leg_int_mask); in qla4_83xx_enable_mbox_intrs()
1303 set_bit(AF_83XX_MBOX_INTR_ON, &ha->flags); in qla4_83xx_enable_mbox_intrs()
1308 void qla4_83xx_enable_intrs(struct scsi_qla_host *ha) in qla4_83xx_enable_intrs() argument
1310 qla4_83xx_enable_mbox_intrs(ha); in qla4_83xx_enable_intrs()
1311 qla4_83xx_enable_iocb_intrs(ha); in qla4_83xx_enable_intrs()
1315 void qla4_83xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd, in qla4_83xx_queue_mbox_cmd() argument
1322 writel(mbx_cmd[i], &ha->qla4_83xx_reg->mailbox_in[i]); in qla4_83xx_queue_mbox_cmd()
1324 writel(mbx_cmd[0], &ha->qla4_83xx_reg->mailbox_in[0]); in qla4_83xx_queue_mbox_cmd()
1329 writel(HINT_MBX_INT_PENDING, &ha->qla4_83xx_reg->host_intr); in qla4_83xx_queue_mbox_cmd()
1332 void qla4_83xx_process_mbox_intr(struct scsi_qla_host *ha, int outcount) in qla4_83xx_process_mbox_intr() argument
1336 intr_status = readl(&ha->qla4_83xx_reg->risc_intr); in qla4_83xx_process_mbox_intr()
1338 ha->mbox_status_count = outcount; in qla4_83xx_process_mbox_intr()
1339 ha->isp_ops->interrupt_service_routine(ha, intr_status); in qla4_83xx_process_mbox_intr()
1347 int qla4_83xx_isp_reset(struct scsi_qla_host *ha) in qla4_83xx_isp_reset() argument
1352 ha->isp_ops->idc_lock(ha); in qla4_83xx_isp_reset()
1353 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE); in qla4_83xx_isp_reset()
1356 qla4_83xx_set_idc_dontreset(ha); in qla4_83xx_isp_reset()
1361 if (qla4_83xx_idc_dontreset(ha) == DONTRESET_BIT0) { in qla4_83xx_isp_reset()
1362 ql4_printk(KERN_ERR, ha, "%s: Reset recovery disabled\n", in qla4_83xx_isp_reset()
1368 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: HW State: NEED RESET\n", in qla4_83xx_isp_reset()
1370 qla4_8xxx_wr_direct(ha, QLA8XXX_CRB_DEV_STATE, in qla4_83xx_isp_reset()
1380 DEBUG2(ql4_printk(KERN_INFO, ha, in qla4_83xx_isp_reset()
1388 if (qla4_83xx_can_perform_reset(ha)) in qla4_83xx_isp_reset()
1389 set_bit(AF_8XXX_RST_OWNER, &ha->flags); in qla4_83xx_isp_reset()
1391 ha->isp_ops->idc_unlock(ha); in qla4_83xx_isp_reset()
1392 rval = qla4_8xxx_device_state_handler(ha); in qla4_83xx_isp_reset()
1394 ha->isp_ops->idc_lock(ha); in qla4_83xx_isp_reset()
1395 qla4_8xxx_clear_rst_ready(ha); in qla4_83xx_isp_reset()
1397 ha->isp_ops->idc_unlock(ha); in qla4_83xx_isp_reset()
1400 clear_bit(AF_FW_RECOVERY, &ha->flags); in qla4_83xx_isp_reset()
1405 static void qla4_83xx_dump_pause_control_regs(struct scsi_qla_host *ha) in qla4_83xx_dump_pause_control_regs() argument
1410 qla4_83xx_rd_reg_indirect(ha, QLA83XX_SRE_SHIM_CONTROL, &val); in qla4_83xx_dump_pause_control_regs()
1411 DEBUG2(ql4_printk(KERN_INFO, ha, "SRE-Shim Ctrl:0x%x\n", val)); in qla4_83xx_dump_pause_control_regs()
1414 DEBUG2(ql4_printk(KERN_INFO, ha, in qla4_83xx_dump_pause_control_regs()
1417 qla4_83xx_rd_reg_indirect(ha, in qla4_83xx_dump_pause_control_regs()
1425 DEBUG2(ql4_printk(KERN_INFO, ha, in qla4_83xx_dump_pause_control_regs()
1428 qla4_83xx_rd_reg_indirect(ha, in qla4_83xx_dump_pause_control_regs()
1436 DEBUG2(ql4_printk(KERN_INFO, ha, in qla4_83xx_dump_pause_control_regs()
1439 qla4_83xx_rd_reg_indirect(ha, in qla4_83xx_dump_pause_control_regs()
1447 DEBUG2(ql4_printk(KERN_INFO, ha, in qla4_83xx_dump_pause_control_regs()
1450 qla4_83xx_rd_reg_indirect(ha, in qla4_83xx_dump_pause_control_regs()
1458 DEBUG2(ql4_printk(KERN_INFO, ha, in qla4_83xx_dump_pause_control_regs()
1461 qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT0_RXB_TC_STATS, &val); in qla4_83xx_dump_pause_control_regs()
1463 qla4_83xx_wr_reg_indirect(ha, QLA83XX_PORT0_RXB_TC_STATS, in qla4_83xx_dump_pause_control_regs()
1465 qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT0_RXB_TC_STATS, &val); in qla4_83xx_dump_pause_control_regs()
1472 DEBUG2(ql4_printk(KERN_INFO, ha, in qla4_83xx_dump_pause_control_regs()
1475 qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT1_RXB_TC_STATS, &val); in qla4_83xx_dump_pause_control_regs()
1477 qla4_83xx_wr_reg_indirect(ha, QLA83XX_PORT1_RXB_TC_STATS, in qla4_83xx_dump_pause_control_regs()
1479 qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT1_RXB_TC_STATS, &val); in qla4_83xx_dump_pause_control_regs()
1485 qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT2_IFB_PAUSE_THRS, &val); in qla4_83xx_dump_pause_control_regs()
1486 qla4_83xx_rd_reg_indirect(ha, QLA83XX_PORT3_IFB_PAUSE_THRS, &val1); in qla4_83xx_dump_pause_control_regs()
1488 DEBUG2(ql4_printk(KERN_INFO, ha, in qla4_83xx_dump_pause_control_regs()
1493 static void __qla4_83xx_disable_pause(struct scsi_qla_host *ha) in __qla4_83xx_disable_pause() argument
1498 qla4_83xx_wr_reg_indirect(ha, QLA83XX_SRE_SHIM_CONTROL, in __qla4_83xx_disable_pause()
1503 qla4_83xx_wr_reg_indirect(ha, in __qla4_83xx_disable_pause()
1507 qla4_83xx_wr_reg_indirect(ha, in __qla4_83xx_disable_pause()
1514 qla4_83xx_wr_reg_indirect(ha, in __qla4_83xx_disable_pause()
1518 qla4_83xx_wr_reg_indirect(ha, in __qla4_83xx_disable_pause()
1523 qla4_83xx_wr_reg_indirect(ha, QLA83XX_PORT2_IFB_PAUSE_THRS, in __qla4_83xx_disable_pause()
1525 qla4_83xx_wr_reg_indirect(ha, QLA83XX_PORT3_IFB_PAUSE_THRS, in __qla4_83xx_disable_pause()
1528 ql4_printk(KERN_INFO, ha, "Disabled pause frames successfully.\n"); in __qla4_83xx_disable_pause()
1539 static void qla4_83xx_eport_init(struct scsi_qla_host *ha) in qla4_83xx_eport_init() argument
1542 qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_REG, 0x0); in qla4_83xx_eport_init()
1543 qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT0, 0x0); in qla4_83xx_eport_init()
1544 qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT1, 0x0); in qla4_83xx_eport_init()
1545 qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT2, 0x0); in qla4_83xx_eport_init()
1546 qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_PORT3, 0x0); in qla4_83xx_eport_init()
1547 qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_SRE_SHIM, 0x0); in qla4_83xx_eport_init()
1548 qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_EPG_SHIM, 0x0); in qla4_83xx_eport_init()
1549 qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_ETHER_PCS, 0x0); in qla4_83xx_eport_init()
1552 qla4_83xx_wr_reg_indirect(ha, QLA83XX_RESET_CONTROL, 0xFF); in qla4_83xx_eport_init()
1554 ql4_printk(KERN_INFO, ha, "EPORT is out of reset.\n"); in qla4_83xx_eport_init()
1557 void qla4_83xx_disable_pause(struct scsi_qla_host *ha) in qla4_83xx_disable_pause() argument
1559 ha->isp_ops->idc_lock(ha); in qla4_83xx_disable_pause()
1561 qla4_83xx_eport_init(ha); in qla4_83xx_disable_pause()
1562 qla4_83xx_dump_pause_control_regs(ha); in qla4_83xx_disable_pause()
1563 __qla4_83xx_disable_pause(ha); in qla4_83xx_disable_pause()
1564 ha->isp_ops->idc_unlock(ha); in qla4_83xx_disable_pause()
1571 int qla4_83xx_is_detached(struct scsi_qla_host *ha) in qla4_83xx_is_detached() argument
1575 drv_active = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DRV_ACTIVE); in qla4_83xx_is_detached()
1577 if (test_bit(AF_INIT_DONE, &ha->flags) && in qla4_83xx_is_detached()
1578 !(drv_active & (1 << ha->func_num))) { in qla4_83xx_is_detached()
1579 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: drv_active = 0x%X\n", in qla4_83xx_is_detached()