Lines Matching +full:reset +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2003-2013 QLogic Corporation
17 return readl((void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_rd_reg()
22 writel(val, (void __iomem *)(ha->nx_pcibase + addr)); in qla4_83xx_wr_reg()
30 qla4_83xx_wr_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num), addr); in qla4_83xx_set_win_base()
31 val = qla4_83xx_rd_reg(ha, QLA83XX_CRB_WIN_FUNC(ha->func_num)); in qla4_83xx_set_win_base()
91 __func__, ha->func_num, lock_owner); in qla4_83xx_flash_lock()
98 qla4_83xx_wr_reg(ha, QLA83XX_FLASH_LOCK_ID, ha->func_num); in qla4_83xx_flash_lock()
169 flash_offset = addr & (QLA83XX_FLASH_SECTOR_SIZE - 1); in qla4_83xx_lockless_flash_read_u32()
188 (QLA83XX_FLASH_SECTOR_SIZE - 1)) { in qla4_83xx_lockless_flash_read_u32()
206 if (flash_offset > (QLA83XX_FLASH_SECTOR_SIZE - 1)) { in qla4_83xx_lockless_flash_read_u32()
262 lockid = ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY); in qla4_83xx_lock_recovery()
269 ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY, in qla4_83xx_lock_recovery()
270 (ha->func_num << 2) | INTENT_TO_RECOVER); in qla4_83xx_lock_recovery()
275 lockid = ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY); in qla4_83xx_lock_recovery()
276 if ((lockid & 0x3C) != (ha->func_num << 2)) in qla4_83xx_lock_recovery()
280 __func__, ha->func_num); in qla4_83xx_lock_recovery()
283 ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY, in qla4_83xx_lock_recovery()
284 (ha->func_num << 2) | PROCEED_TO_RECOVER); in qla4_83xx_lock_recovery()
287 ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCK_ID, 0xFF); in qla4_83xx_lock_recovery()
288 ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_UNLOCK); in qla4_83xx_lock_recovery()
290 /* Clear bits 0-5 in IDC_RECOVERY register*/ in qla4_83xx_lock_recovery()
291 ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCKRECOVERY, 0); in qla4_83xx_lock_recovery()
294 lock = ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_LOCK); in qla4_83xx_lock_recovery()
296 lockid = ha->isp_ops->rd_reg_direct(ha, QLA83XX_DRV_LOCK_ID); in qla4_83xx_lock_recovery()
297 lockid = ((lockid + (1 << 8)) & ~0xFF) | ha->func_num; in qla4_83xx_lock_recovery()
298 ha->isp_ops->wr_reg_direct(ha, QLA83XX_DRV_LOCK_ID, lockid); in qla4_83xx_lock_recovery()
322 /* Increment Counter (8-31) and update func_num (0-7) on in qla4_83xx_drv_lock()
325 lock_id = ((lock_id + (1 << 8)) & ~0xFF) | ha->func_num; in qla4_83xx_drv_lock()
333 first_owner = ha->isp_ops->rd_reg_direct(ha, in qla4_83xx_drv_lock()
342 __func__, ha->func_num, func_num, lock_cnt, in qla4_83xx_drv_lock()
351 __func__, ha->func_num); in qla4_83xx_drv_lock()
360 __func__, ha->func_num); in qla4_83xx_drv_lock()
366 __func__, ha->func_num); in qla4_83xx_drv_lock()
382 if ((id & 0xFF) != ha->func_num) { in qla4_83xx_drv_unlock()
384 __func__, ha->func_num, (id & 0xFF)); in qla4_83xx_drv_unlock()
388 /* Keep lock counter value, update the ha->func_num to 0xFF */ in qla4_83xx_drv_unlock()
423 /*-------------------------IDC State Machine ---------------------*/
453 ha->reg_tbl[QLA8XXX_CRB_DEV_PART_INFO]); in qla4_83xx_can_perform_reset()
455 drv_active = qla4_83xx_rd_reg(ha, ha->reg_tbl[QLA8XXX_CRB_DRV_ACTIVE]); in qla4_83xx_can_perform_reset()
458 * Lower 2 bits - device type, Upper 2 bits - physical port number */ in qla4_83xx_can_perform_reset()
490 /* NIC, iSCSI and FCOE are the Reset owners based on order, NIC gets in qla4_83xx_can_perform_reset()
493 if (!nic_present && (ha->func_num == iscsi_func_low)) { in qla4_83xx_can_perform_reset()
495 "%s: can reset - NIC not present and lower iSCSI function is %d\n", in qla4_83xx_can_perform_reset()
496 __func__, ha->func_num)); in qla4_83xx_can_perform_reset()
504 * qla4_83xx_need_reset_handler - Code to start reset sequence
517 if (!test_bit(AF_8XXX_RST_OWNER, &ha->flags)) { in qla4_83xx_need_reset_handler()
518 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: reset acknowledged\n", in qla4_83xx_need_reset_handler()
522 /* Non-reset owners ACK Reset and wait for device INIT state in qla4_83xx_need_reset_handler()
523 * as part of Reset Recovery by Reset Owner */ in qla4_83xx_need_reset_handler()
524 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); in qla4_83xx_need_reset_handler()
528 ql4_printk(KERN_INFO, ha, "%s: Non Reset owner dev init timeout\n", in qla4_83xx_need_reset_handler()
533 ha->isp_ops->idc_unlock(ha); in qla4_83xx_need_reset_handler()
535 ha->isp_ops->idc_lock(ha); in qla4_83xx_need_reset_handler()
542 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); in qla4_83xx_need_reset_handler()
551 ql4_printk(KERN_INFO, ha, "%s: %s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n", in qla4_83xx_need_reset_handler()
557 ha->isp_ops->idc_unlock(ha); in qla4_83xx_need_reset_handler()
559 ha->isp_ops->idc_lock(ha); in qla4_83xx_need_reset_handler()
568 ql4_printk(KERN_INFO, ha, "%s: Reset_owner turning off drv_active of non-acking function 0x%x\n", in qla4_83xx_need_reset_handler()
575 clear_bit(AF_8XXX_RST_OWNER, &ha->flags); in qla4_83xx_need_reset_handler()
576 /* Start Reset Recovery */ in qla4_83xx_need_reset_handler()
588 ha->nx_dev_init_timeout = idc_params & 0xFFFF; in qla4_83xx_get_idc_param()
589 ha->nx_reset_timeout = (idc_params >> 16) & 0xFFFF; in qla4_83xx_get_idc_param()
591 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT; in qla4_83xx_get_idc_param()
592 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT; in qla4_83xx_get_idc_param()
596 "%s: ha->nx_dev_init_timeout = %d, ha->nx_reset_timeout = %d\n", in qla4_83xx_get_idc_param()
597 __func__, ha->nx_dev_init_timeout, in qla4_83xx_get_idc_param()
598 ha->nx_reset_timeout)); in qla4_83xx_get_idc_param()
601 /*-------------------------Reset Sequence Functions-----------------------*/
607 if (!ha->reset_tmplt.buff) { in qla4_83xx_dump_reset_seq_hdr()
613 phdr = ha->reset_tmplt.buff; in qla4_83xx_dump_reset_seq_hdr()
616 …"Reset Template: 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n… in qla4_83xx_dump_reset_seq_hdr()
693 } while (--retries); in qla4_83xx_check_cmd_peg_status()
699 * qla4_83xx_poll_reg - Poll the given CRB addr for duration msecs till
733 } while (retries--); in qla4_83xx_poll_reg()
737 ha->reset_tmplt.seq_error++; in qla4_83xx_poll_reg()
748 uint16_t *buff = (uint16_t *)ha->reset_tmplt.buff; in qla4_83xx_reset_seq_checksum_test()
749 int u16_count = ha->reset_tmplt.hdr->size / sizeof(uint16_t); in qla4_83xx_reset_seq_checksum_test()
752 while (u16_count-- > 0) in qla4_83xx_reset_seq_checksum_test()
762 ql4_printk(KERN_ERR, ha, "%s: Reset seq checksum failed\n", in qla4_83xx_reset_seq_checksum_test()
771 * qla4_83xx_read_reset_template - Read Reset Template from Flash
780 ha->reset_tmplt.seq_error = 0; in qla4_83xx_read_reset_template()
781 ha->reset_tmplt.buff = vmalloc(QLA83XX_RESTART_TEMPLATE_SIZE); in qla4_83xx_read_reset_template()
782 if (ha->reset_tmplt.buff == NULL) { in qla4_83xx_read_reset_template()
783 ql4_printk(KERN_ERR, ha, "%s: Failed to allocate reset template resources\n", in qla4_83xx_read_reset_template()
788 p_buff = ha->reset_tmplt.buff; in qla4_83xx_read_reset_template()
802 ql4_printk(KERN_ERR, ha, "%s: Failed to read reset template\n", in qla4_83xx_read_reset_template()
807 ha->reset_tmplt.hdr = in qla4_83xx_read_reset_template()
808 (struct qla4_83xx_reset_template_hdr *)ha->reset_tmplt.buff; in qla4_83xx_read_reset_template()
811 tmplt_hdr_size = ha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t); in qla4_83xx_read_reset_template()
813 (ha->reset_tmplt.hdr->signature != RESET_TMPLT_HDR_SIGNATURE)) { in qla4_83xx_read_reset_template()
819 addr = QLA83XX_RESET_TEMPLATE_ADDR + ha->reset_tmplt.hdr->hdr_size; in qla4_83xx_read_reset_template()
820 p_buff = ha->reset_tmplt.buff + ha->reset_tmplt.hdr->hdr_size; in qla4_83xx_read_reset_template()
821 tmplt_hdr_def_size = (ha->reset_tmplt.hdr->size - in qla4_83xx_read_reset_template()
822 ha->reset_tmplt.hdr->hdr_size) / sizeof(uint32_t); in qla4_83xx_read_reset_template()
826 __func__, ha->reset_tmplt.hdr->size)); in qla4_83xx_read_reset_template()
832 ql4_printk(KERN_ERR, ha, "%s: Failed to read reset template\n", in qla4_83xx_read_reset_template()
839 ql4_printk(KERN_ERR, ha, "%s: Reset Seq checksum failed!\n", in qla4_83xx_read_reset_template()
844 "%s: Reset Seq checksum passed, Get stop, start and init seq offsets\n", in qla4_83xx_read_reset_template()
848 ha->reset_tmplt.init_offset = ha->reset_tmplt.buff + in qla4_83xx_read_reset_template()
849 ha->reset_tmplt.hdr->init_seq_offset; in qla4_83xx_read_reset_template()
850 ha->reset_tmplt.start_offset = ha->reset_tmplt.buff + in qla4_83xx_read_reset_template()
851 ha->reset_tmplt.hdr->start_seq_offset; in qla4_83xx_read_reset_template()
852 ha->reset_tmplt.stop_offset = ha->reset_tmplt.buff + in qla4_83xx_read_reset_template()
853 ha->reset_tmplt.hdr->hdr_size; in qla4_83xx_read_reset_template()
859 vfree(ha->reset_tmplt.buff); in qla4_83xx_read_reset_template()
866 * qla4_83xx_read_write_crb_reg - Read from raddr and write value to waddr.
882 * qla4_83xx_rmw_crb_reg - Read Modify Write crb register
898 if (p_rmw_hdr->index_a) in qla4_83xx_rmw_crb_reg()
899 value = ha->reset_tmplt.array[p_rmw_hdr->index_a]; in qla4_83xx_rmw_crb_reg()
903 value &= p_rmw_hdr->test_mask; in qla4_83xx_rmw_crb_reg()
904 value <<= p_rmw_hdr->shl; in qla4_83xx_rmw_crb_reg()
905 value >>= p_rmw_hdr->shr; in qla4_83xx_rmw_crb_reg()
906 value |= p_rmw_hdr->or_value; in qla4_83xx_rmw_crb_reg()
907 value ^= p_rmw_hdr->xor_value; in qla4_83xx_rmw_crb_reg()
923 for (i = 0; i < p_hdr->count; i++, p_entry++) { in qla4_83xx_write_list()
924 qla4_83xx_wr_reg_indirect(ha, p_entry->arg1, p_entry->arg2); in qla4_83xx_write_list()
925 if (p_hdr->delay) in qla4_83xx_write_list()
926 udelay((uint32_t)(p_hdr->delay)); in qla4_83xx_write_list()
939 for (i = 0; i < p_hdr->count; i++, p_entry++) { in qla4_83xx_read_write_list()
940 qla4_83xx_read_write_crb_reg(ha, p_entry->arg1, p_entry->arg2); in qla4_83xx_read_write_list()
941 if (p_hdr->delay) in qla4_83xx_read_write_list()
942 udelay((uint32_t)(p_hdr->delay)); in qla4_83xx_read_write_list()
949 long delay; in qla4_83xx_poll_list() local
963 delay = (long)p_hdr->delay; in qla4_83xx_poll_list()
964 if (!delay) { in qla4_83xx_poll_list()
965 for (i = 0; i < p_hdr->count; i++, p_entry++) { in qla4_83xx_poll_list()
966 qla4_83xx_poll_reg(ha, p_entry->arg1, delay, in qla4_83xx_poll_list()
967 p_poll->test_mask, in qla4_83xx_poll_list()
968 p_poll->test_value); in qla4_83xx_poll_list()
971 for (i = 0; i < p_hdr->count; i++, p_entry++) { in qla4_83xx_poll_list()
972 if (qla4_83xx_poll_reg(ha, p_entry->arg1, delay, in qla4_83xx_poll_list()
973 p_poll->test_mask, in qla4_83xx_poll_list()
974 p_poll->test_value)) { in qla4_83xx_poll_list()
975 qla4_83xx_rd_reg_indirect(ha, p_entry->arg1, in qla4_83xx_poll_list()
977 qla4_83xx_rd_reg_indirect(ha, p_entry->arg2, in qla4_83xx_poll_list()
987 long delay; in qla4_83xx_poll_write_list() local
996 delay = (long)p_hdr->delay; in qla4_83xx_poll_write_list()
998 for (i = 0; i < p_hdr->count; i++, p_entry++) { in qla4_83xx_poll_write_list()
999 qla4_83xx_wr_reg_indirect(ha, p_entry->dr_addr, in qla4_83xx_poll_write_list()
1000 p_entry->dr_value); in qla4_83xx_poll_write_list()
1001 qla4_83xx_wr_reg_indirect(ha, p_entry->ar_addr, in qla4_83xx_poll_write_list()
1002 p_entry->ar_value); in qla4_83xx_poll_write_list()
1003 if (delay) { in qla4_83xx_poll_write_list()
1004 if (qla4_83xx_poll_reg(ha, p_entry->ar_addr, delay, in qla4_83xx_poll_write_list()
1005 p_poll->test_mask, in qla4_83xx_poll_write_list()
1006 p_poll->test_value)) { in qla4_83xx_poll_write_list()
1010 ha->reset_tmplt.seq_index)); in qla4_83xx_poll_write_list()
1028 for (i = 0; i < p_hdr->count; i++, p_entry++) { in qla4_83xx_read_modify_write()
1029 qla4_83xx_rmw_crb_reg(ha, p_entry->arg1, p_entry->arg2, in qla4_83xx_read_modify_write()
1031 if (p_hdr->delay) in qla4_83xx_read_modify_write()
1032 udelay((uint32_t)(p_hdr->delay)); in qla4_83xx_read_modify_write()
1039 if (p_hdr->delay) in qla4_83xx_pause()
1040 mdelay((uint32_t)((long)p_hdr->delay)); in qla4_83xx_pause()
1046 long delay; in qla4_83xx_poll_read_list() local
1057 delay = (long)p_hdr->delay; in qla4_83xx_poll_read_list()
1059 for (i = 0; i < p_hdr->count; i++, p_entry++) { in qla4_83xx_poll_read_list()
1060 qla4_83xx_wr_reg_indirect(ha, p_entry->ar_addr, in qla4_83xx_poll_read_list()
1061 p_entry->ar_value); in qla4_83xx_poll_read_list()
1062 if (delay) { in qla4_83xx_poll_read_list()
1063 if (qla4_83xx_poll_reg(ha, p_entry->ar_addr, delay, in qla4_83xx_poll_read_list()
1064 p_poll->test_mask, in qla4_83xx_poll_read_list()
1065 p_poll->test_value)) { in qla4_83xx_poll_read_list()
1069 ha->reset_tmplt.seq_index)); in qla4_83xx_poll_read_list()
1071 index = ha->reset_tmplt.array_index; in qla4_83xx_poll_read_list()
1072 qla4_83xx_rd_reg_indirect(ha, p_entry->dr_addr, in qla4_83xx_poll_read_list()
1074 ha->reset_tmplt.array[index++] = value; in qla4_83xx_poll_read_list()
1077 ha->reset_tmplt.array_index = 1; in qla4_83xx_poll_read_list()
1086 ha->reset_tmplt.seq_end = 1; in qla4_83xx_seq_end()
1092 ha->reset_tmplt.template_end = 1; in qla4_83xx_template_end()
1094 if (ha->reset_tmplt.seq_error == 0) { in qla4_83xx_template_end()
1096 "%s: Reset sequence completed SUCCESSFULLY.\n", in qla4_83xx_template_end()
1099 ql4_printk(KERN_ERR, ha, "%s: Reset sequence completed with some timeout errors.\n", in qla4_83xx_template_end()
1105 * qla4_83xx_process_reset_template - Process reset template.
1107 * Process all entries in reset template till entry with SEQ_END opcode,
1108 * which indicates end of the reset template processing. Each entry has a
1109 * Reset Entry header, entry opcode/command, with size of the entry, number
1110 * of entries in sub-sequence and delay in microsecs or timeout in millisecs.
1113 * @p_buff : Common reset entry header.
1122 ha->reset_tmplt.seq_end = 0; in qla4_83xx_process_reset_template()
1123 ha->reset_tmplt.template_end = 0; in qla4_83xx_process_reset_template()
1124 entries = ha->reset_tmplt.hdr->entries; in qla4_83xx_process_reset_template()
1125 index = ha->reset_tmplt.seq_index; in qla4_83xx_process_reset_template()
1127 for (; (!ha->reset_tmplt.seq_end) && (index < entries); index++) { in qla4_83xx_process_reset_template()
1130 switch (p_hdr->cmd) { in qla4_83xx_process_reset_template()
1162 __func__, p_hdr->cmd, index); in qla4_83xx_process_reset_template()
1167 p_entry += p_hdr->size; in qla4_83xx_process_reset_template()
1170 ha->reset_tmplt.seq_index = index; in qla4_83xx_process_reset_template()
1175 ha->reset_tmplt.seq_index = 0; in qla4_83xx_process_stop_seq()
1176 qla4_83xx_process_reset_template(ha, ha->reset_tmplt.stop_offset); in qla4_83xx_process_stop_seq()
1178 if (ha->reset_tmplt.seq_end != 1) in qla4_83xx_process_stop_seq()
1179 ql4_printk(KERN_ERR, ha, "%s: Abrupt STOP Sub-Sequence end.\n", in qla4_83xx_process_stop_seq()
1185 qla4_83xx_process_reset_template(ha, ha->reset_tmplt.start_offset); in qla4_83xx_process_start_seq()
1187 if (ha->reset_tmplt.template_end != 1) in qla4_83xx_process_start_seq()
1188 ql4_printk(KERN_ERR, ha, "%s: Abrupt START Sub-Sequence end.\n", in qla4_83xx_process_start_seq()
1194 qla4_83xx_process_reset_template(ha, ha->reset_tmplt.init_offset); in qla4_83xx_process_init_seq()
1196 if (ha->reset_tmplt.seq_end != 1) in qla4_83xx_process_init_seq()
1197 ql4_printk(KERN_ERR, ha, "%s: Abrupt INIT Sub-Sequence end.\n", in qla4_83xx_process_init_seq()
1217 ql4_printk(KERN_INFO, ha, "%s: Graceful RESET: Not collecting minidump\n", in qla4_83xx_restart()
1261 /*----------------------Interrupt Related functions ---------------------*/
1265 if (test_and_clear_bit(AF_83XX_IOCB_INTR_ON, &ha->flags)) in qla4_83xx_disable_iocb_intrs()
1273 if (test_and_clear_bit(AF_83XX_MBOX_INTR_ON, &ha->flags)) { in qla4_83xx_disable_mbox_intrs()
1274 ret = readl(&ha->qla4_83xx_reg->mbox_int); in qla4_83xx_disable_mbox_intrs()
1276 writel(mb_int, &ha->qla4_83xx_reg->mbox_int); in qla4_83xx_disable_mbox_intrs()
1277 writel(1, &ha->qla4_83xx_reg->leg_int_mask); in qla4_83xx_disable_mbox_intrs()
1289 if (!test_bit(AF_83XX_IOCB_INTR_ON, &ha->flags)) { in qla4_83xx_enable_iocb_intrs()
1291 set_bit(AF_83XX_IOCB_INTR_ON, &ha->flags); in qla4_83xx_enable_iocb_intrs()
1299 if (!test_bit(AF_83XX_MBOX_INTR_ON, &ha->flags)) { in qla4_83xx_enable_mbox_intrs()
1301 writel(mb_int, &ha->qla4_83xx_reg->mbox_int); in qla4_83xx_enable_mbox_intrs()
1302 writel(0, &ha->qla4_83xx_reg->leg_int_mask); in qla4_83xx_enable_mbox_intrs()
1303 set_bit(AF_83XX_MBOX_INTR_ON, &ha->flags); in qla4_83xx_enable_mbox_intrs()
1322 writel(mbx_cmd[i], &ha->qla4_83xx_reg->mailbox_in[i]); in qla4_83xx_queue_mbox_cmd()
1324 writel(mbx_cmd[0], &ha->qla4_83xx_reg->mailbox_in[0]); in qla4_83xx_queue_mbox_cmd()
1329 writel(HINT_MBX_INT_PENDING, &ha->qla4_83xx_reg->host_intr); in qla4_83xx_queue_mbox_cmd()
1336 intr_status = readl(&ha->qla4_83xx_reg->risc_intr); in qla4_83xx_process_mbox_intr()
1338 ha->mbox_status_count = outcount; in qla4_83xx_process_mbox_intr()
1339 ha->isp_ops->interrupt_service_routine(ha, intr_status); in qla4_83xx_process_mbox_intr()
1344 * qla4_83xx_isp_reset - Resets ISP and aborts all outstanding commands.
1352 ha->isp_ops->idc_lock(ha); in qla4_83xx_isp_reset()
1359 /* If IDC_CTRL DONTRESETHBA_BIT0 is set dont do reset in qla4_83xx_isp_reset()
1362 ql4_printk(KERN_ERR, ha, "%s: Reset recovery disabled\n", in qla4_83xx_isp_reset()
1368 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: HW State: NEED RESET\n", in qla4_83xx_isp_reset()
1375 * Reset,irrespective of ql4xdontresethba. This is to allow a in qla4_83xx_isp_reset()
1376 * non-reset-owner to force a reset. Non-reset-owner sets in qla4_83xx_isp_reset()
1377 * the IDC_CTRL BIT0 to prevent Reset-owner from doing a Reset in qla4_83xx_isp_reset()
1378 * and then forces a Reset by setting device_state to in qla4_83xx_isp_reset()
1385 /* For ISP8324 and ISP8042, Reset owner is NIC, iSCSI or FCOE based on in qla4_83xx_isp_reset()
1387 * setting NEED_RESET, may not be the Reset owner. */ in qla4_83xx_isp_reset()
1389 set_bit(AF_8XXX_RST_OWNER, &ha->flags); in qla4_83xx_isp_reset()
1391 ha->isp_ops->idc_unlock(ha); in qla4_83xx_isp_reset()
1394 ha->isp_ops->idc_lock(ha); in qla4_83xx_isp_reset()
1397 ha->isp_ops->idc_unlock(ha); in qla4_83xx_isp_reset()
1400 clear_bit(AF_FW_RECOVERY, &ha->flags); in qla4_83xx_isp_reset()
1411 DEBUG2(ql4_printk(KERN_INFO, ha, "SRE-Shim Ctrl:0x%x\n", val)); in qla4_83xx_dump_pause_control_regs()
1460 for (i = 7; i >= 0; i--) { in qla4_83xx_dump_pause_control_regs()
1462 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */ in qla4_83xx_dump_pause_control_regs()
1474 for (i = 7; i >= 0; i--) { in qla4_83xx_dump_pause_control_regs()
1476 val &= ~(0x7 << 29); /* Reset bits 29 to 31 */ in qla4_83xx_dump_pause_control_regs()
1489 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n", in qla4_83xx_dump_pause_control_regs()
1497 /* set SRE-Shim Control Register */ in __qla4_83xx_disable_pause()
1532 * qla4_83xx_eport_init - Initialize EPort.
1535 * If EPort hardware is in reset state before disabling pause, there would be
1551 /* Write any value to Reset Control register */ in qla4_83xx_eport_init()
1554 ql4_printk(KERN_INFO, ha, "EPORT is out of reset.\n"); in qla4_83xx_eport_init()
1559 ha->isp_ops->idc_lock(ha); in qla4_83xx_disable_pause()
1560 /* Before disabling pause frames, ensure that eport is not in reset */ in qla4_83xx_disable_pause()
1564 ha->isp_ops->idc_unlock(ha); in qla4_83xx_disable_pause()
1568 * qla4_83xx_is_detached - Check if we are marked invisible.
1577 if (test_bit(AF_INIT_DONE, &ha->flags) && in qla4_83xx_is_detached()
1578 !(drv_active & (1 << ha->func_num))) { in qla4_83xx_is_detached()