Lines Matching +full:0 +full:xb00d
15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
16 ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
18 ((addr >> 25) & 0x3ff))
19 #define MS_WIN(addr) (addr & 0x0ffc0000)
20 #define QLA82XX_PCI_MN_2M (0)
21 #define QLA82XX_PCI_MS_2M (0x80000)
22 #define QLA82XX_PCI_OCM0_2M (0xc0000)
23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
25 #define BLOCK_PROTECT_BITS 0x0F
28 #define CRB_BLK(off) ((off >> 20) & 0x3f)
29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30 #define CRB_WINDOW_2M (0x130060)
31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
33 ((off) & 0xf0000))
34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
35 #define CRB_INDIRECT_2M (0x1e0000UL)
46 0x410000A8, 0x410000AC,
47 0x410000B8, 0x410000BC
111 {{{0, 0, 0, 0} } },
112 {{{1, 0x0100000, 0x0102000, 0x120000},
113 {1, 0x0110000, 0x0120000, 0x130000},
114 {1, 0x0120000, 0x0122000, 0x124000},
115 {1, 0x0130000, 0x0132000, 0x126000},
116 {1, 0x0140000, 0x0142000, 0x128000},
117 {1, 0x0150000, 0x0152000, 0x12a000},
118 {1, 0x0160000, 0x0170000, 0x110000},
119 {1, 0x0170000, 0x0172000, 0x12e000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {1, 0x01e0000, 0x01e0800, 0x122000},
127 {0, 0x0000000, 0x0000000, 0x000000} } } ,
128 {{{1, 0x0200000, 0x0210000, 0x180000} } },
129 {{{0, 0, 0, 0} } },
130 {{{1, 0x0400000, 0x0401000, 0x169000} } },
131 {{{1, 0x0500000, 0x0510000, 0x140000} } },
132 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
133 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
134 {{{1, 0x0800000, 0x0802000, 0x170000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {1, 0x08f0000, 0x08f2000, 0x172000} } },
150 {{{1, 0x0900000, 0x0902000, 0x174000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {1, 0x09f0000, 0x09f2000, 0x176000} } },
166 {{{0, 0x0a00000, 0x0a02000, 0x178000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
182 {{{0, 0x0b00000, 0x0b02000, 0x17c000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {0, 0x0000000, 0x0000000, 0x000000},
194 {0, 0x0000000, 0x0000000, 0x000000},
195 {0, 0x0000000, 0x0000000, 0x000000},
196 {0, 0x0000000, 0x0000000, 0x000000},
197 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
198 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
199 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
200 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
201 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
202 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
203 {{{1, 0x1100000, 0x1101000, 0x160000} } },
204 {{{1, 0x1200000, 0x1201000, 0x161000} } },
205 {{{1, 0x1300000, 0x1301000, 0x162000} } },
206 {{{1, 0x1400000, 0x1401000, 0x163000} } },
207 {{{1, 0x1500000, 0x1501000, 0x165000} } },
208 {{{1, 0x1600000, 0x1601000, 0x166000} } },
209 {{{0, 0, 0, 0} } },
210 {{{0, 0, 0, 0} } },
211 {{{0, 0, 0, 0} } },
212 {{{0, 0, 0, 0} } },
213 {{{0, 0, 0, 0} } },
214 {{{0, 0, 0, 0} } },
215 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
216 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
217 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
218 {{{0} } },
219 {{{1, 0x2100000, 0x2102000, 0x120000},
220 {1, 0x2110000, 0x2120000, 0x130000},
221 {1, 0x2120000, 0x2122000, 0x124000},
222 {1, 0x2130000, 0x2132000, 0x126000},
223 {1, 0x2140000, 0x2142000, 0x128000},
224 {1, 0x2150000, 0x2152000, 0x12a000},
225 {1, 0x2160000, 0x2170000, 0x110000},
226 {1, 0x2170000, 0x2172000, 0x12e000},
227 {0, 0x0000000, 0x0000000, 0x000000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000},
230 {0, 0x0000000, 0x0000000, 0x000000},
231 {0, 0x0000000, 0x0000000, 0x000000},
232 {0, 0x0000000, 0x0000000, 0x000000},
233 {0, 0x0000000, 0x0000000, 0x000000},
234 {0, 0x0000000, 0x0000000, 0x000000} } },
235 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
236 {{{0} } },
237 {{{0} } },
238 {{{0} } },
239 {{{0} } },
240 {{{0} } },
241 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
242 {{{1, 0x2900000, 0x2901000, 0x16b000} } },
243 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
244 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
245 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
246 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
247 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
248 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
249 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
250 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
251 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
252 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
253 {{{0} } },
254 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
255 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
256 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
257 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
258 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
259 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
260 {{{0} } },
261 {{{0} } },
262 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
263 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
264 {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
271 0,
275 0,
298 0,
301 0,
303 0,
306 0,
307 0,
308 0,
309 0,
310 0,
312 0,
323 0,
328 0,
332 0,
334 0,
374 ql_dbg(ql_dbg_p3p, vha, 0xb000, in qla82xx_pci_set_crbwindow_2M()
375 "%s: Written crbwin (0x%x) " in qla82xx_pci_set_crbwindow_2M()
376 "!= Read crbwin (0x%x), off=0x%lx.\n", in qla82xx_pci_set_crbwindow_2M()
394 return 0; in qla82xx_pci_get_crb_addr_2M()
407 return 0; in qla82xx_pci_get_crb_addr_2M()
417 int done = 0, timeout = 0; in qla82xx_crb_win_lock()
429 return 0; in qla82xx_crb_win_lock()
436 unsigned long flags = 0; in qla82xx_wr_32()
459 return 0; in qla82xx_wr_32()
466 unsigned long flags = 0; in qla82xx_rd_32()
496 int done = 0, timeout = 0; in qla82xx_idc_lock()
512 for (i = 0; i < 20; i++) in qla82xx_idc_lock()
517 return 0; in qla82xx_idc_lock()
538 return 0; in qla82xx_pci_mem_bound_check()
562 ql_dbg(ql_dbg_p3p, vha, 0xb003, in qla82xx_pci_set_window()
563 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n", in qla82xx_pci_set_window()
571 if ((addr & 0x00ff800) == 0xff800) { in qla82xx_pci_set_window()
572 ql_log(ql_log_warn, vha, 0xb004, in qla82xx_pci_set_window()
582 temp1 = ((window & 0x1FF) << 7) | in qla82xx_pci_set_window()
583 ((window & 0x0FFFE0000) >> 17); in qla82xx_pci_set_window()
585 ql_log(ql_log_warn, vha, 0xb005, in qla82xx_pci_set_window()
586 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n", in qla82xx_pci_set_window()
601 ql_log(ql_log_warn, vha, 0xb006, in qla82xx_pci_set_window()
602 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n", in qla82xx_pci_set_window()
612 (qla82xx_pci_set_window_warning_count%64 == 0)) { in qla82xx_pci_set_window()
613 ql_log(ql_log_warn, vha, 0xb007, in qla82xx_pci_set_window()
643 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; in qla82xx_pci_is_same_window()
647 return 0; in qla82xx_pci_is_same_window()
655 int ret = 0; in qla82xx_pci_mem_read_direct()
670 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { in qla82xx_pci_mem_read_direct()
672 ql_log(ql_log_fatal, vha, 0xb008, in qla82xx_pci_mem_read_direct()
674 "access, offset is 0x%llx.\n", in qla82xx_pci_mem_read_direct()
680 mem_base = pci_resource_start(ha->pdev, 0); in qla82xx_pci_mem_read_direct()
690 *(u8 *)data = 0; in qla82xx_pci_mem_read_direct()
727 int ret = 0; in qla82xx_pci_mem_write_direct()
742 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { in qla82xx_pci_mem_write_direct()
744 ql_log(ql_log_fatal, vha, 0xb009, in qla82xx_pci_mem_write_direct()
746 "access, offset is 0x%llx.\n", in qla82xx_pci_mem_write_direct()
752 mem_base = pci_resource_start(ha->pdev, 0); in qla82xx_pci_mem_write_direct()
802 base_addr = addr & 0xfff00000; in qla82xx_decode_crb_addr()
803 offset = addr & 0x000fffff; in qla82xx_decode_crb_addr()
805 for (i = 0; i < MAX_CRB_XFORM; i++) { in qla82xx_decode_crb_addr()
822 int done = 0, timeout = 0; in qla82xx_rom_lock()
823 uint32_t lock_owner = 0; in qla82xx_rom_lock()
833 ql_dbg(ql_dbg_p3p, vha, 0xb157, in qla82xx_rom_lock()
841 return 0; in qla82xx_rom_lock()
847 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff); in qla82xx_rom_unlock()
854 long timeout = 0; in qla82xx_wait_rom_busy()
855 long done = 0 ; in qla82xx_wait_rom_busy()
858 while (done == 0) { in qla82xx_wait_rom_busy()
863 ql_dbg(ql_dbg_p3p, vha, 0xb00a, in qla82xx_wait_rom_busy()
869 return 0; in qla82xx_wait_rom_busy()
875 long timeout = 0; in qla82xx_wait_rom_done()
876 long done = 0 ; in qla82xx_wait_rom_done()
879 while (done == 0) { in qla82xx_wait_rom_done()
884 ql_dbg(ql_dbg_p3p, vha, 0xb00b, in qla82xx_wait_rom_done()
890 return 0; in qla82xx_wait_rom_done()
896 uint32_t off_value, rval = 0; in qla82xx_md_rw_32()
898 wrt_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000); in qla82xx_md_rw_32()
902 off_value = (off & 0x0000FFFF); in qla82xx_md_rw_32()
918 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1); in qla82xx_do_rom_fast_read()
920 (addr & 0x0000FFFF), 0, 0); in qla82xx_do_rom_fast_read()
922 return 0; in qla82xx_do_rom_fast_read()
928 int ret, loops = 0; in qla82xx_rom_fast_read()
929 uint32_t lock_owner = 0; in qla82xx_rom_fast_read()
932 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { in qla82xx_rom_fast_read()
939 ql_log(ql_log_fatal, vha, 0x00b9, in qla82xx_rom_fast_read()
957 ql_log(ql_log_warn, vha, 0xb00c, in qla82xx_read_status_reg()
962 return 0; in qla82xx_read_status_reg()
972 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); in qla82xx_flash_wait_write_finish()
973 for (i = 0; i < 50000; i++) { in qla82xx_flash_wait_write_finish()
975 if (ret < 0 || (val & 1) == 0) in qla82xx_flash_wait_write_finish()
980 ql_log(ql_log_warn, vha, 0xb00d, in qla82xx_flash_wait_write_finish()
991 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); in qla82xx_flash_set_write_enable()
996 if (qla82xx_read_status_reg(ha, &val) != 0) in qla82xx_flash_set_write_enable()
1000 return 0; in qla82xx_flash_set_write_enable()
1011 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); in qla82xx_write_status_reg()
1013 ql_log(ql_log_warn, vha, 0xb00e, in qla82xx_write_status_reg()
1027 ql_log(ql_log_warn, vha, 0xb00f, in qla82xx_write_disable_flash()
1031 return 0; in qla82xx_write_disable_flash()
1037 int loops = 0; in ql82xx_rom_lock_d()
1038 uint32_t lock_owner = 0; in ql82xx_rom_lock_d()
1041 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { in ql82xx_rom_lock_d()
1048 ql_log(ql_log_warn, vha, 0xb010, in ql82xx_rom_lock_d()
1052 return 0; in ql82xx_rom_lock_d()
1059 int ret = 0; in qla82xx_write_flash_dword()
1063 if (ret < 0) { in qla82xx_write_flash_dword()
1064 ql_log(ql_log_warn, vha, 0xb011, in qla82xx_write_flash_dword()
1070 if (ret < 0) in qla82xx_write_flash_dword()
1079 ql_log(ql_log_warn, vha, 0xb012, in qla82xx_write_flash_dword()
1114 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); in qla82xx_pinit_from_rom()
1115 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); in qla82xx_pinit_from_rom()
1116 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); in qla82xx_pinit_from_rom()
1117 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); in qla82xx_pinit_from_rom()
1118 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); in qla82xx_pinit_from_rom()
1119 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); in qla82xx_pinit_from_rom()
1122 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); in qla82xx_pinit_from_rom()
1124 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); in qla82xx_pinit_from_rom()
1126 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); in qla82xx_pinit_from_rom()
1128 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); in qla82xx_pinit_from_rom()
1130 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); in qla82xx_pinit_from_rom()
1132 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); in qla82xx_pinit_from_rom()
1135 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); in qla82xx_pinit_from_rom()
1136 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); in qla82xx_pinit_from_rom()
1139 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); in qla82xx_pinit_from_rom()
1142 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); in qla82xx_pinit_from_rom()
1143 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); in qla82xx_pinit_from_rom()
1144 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); in qla82xx_pinit_from_rom()
1145 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); in qla82xx_pinit_from_rom()
1146 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); in qla82xx_pinit_from_rom()
1147 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); in qla82xx_pinit_from_rom()
1150 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); in qla82xx_pinit_from_rom()
1151 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); in qla82xx_pinit_from_rom()
1152 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); in qla82xx_pinit_from_rom()
1153 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); in qla82xx_pinit_from_rom()
1154 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); in qla82xx_pinit_from_rom()
1160 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); in qla82xx_pinit_from_rom()
1162 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); in qla82xx_pinit_from_rom()
1166 * Offset 0: Contain signature (0xcafecafe) in qla82xx_pinit_from_rom()
1170 n = 0; in qla82xx_pinit_from_rom()
1171 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || in qla82xx_pinit_from_rom()
1172 qla82xx_rom_fast_read(ha, 4, &n) != 0) { in qla82xx_pinit_from_rom()
1173 ql_log(ql_log_fatal, vha, 0x006e, in qla82xx_pinit_from_rom()
1181 offset = n & 0xffffU; in qla82xx_pinit_from_rom()
1182 n = (n >> 16) & 0xffffU; in qla82xx_pinit_from_rom()
1186 ql_log(ql_log_fatal, vha, 0x0071, in qla82xx_pinit_from_rom()
1187 "Card flash not initialized:n=0x%x.\n", n); in qla82xx_pinit_from_rom()
1191 ql_log(ql_log_info, vha, 0x0072, in qla82xx_pinit_from_rom()
1196 ql_log(ql_log_fatal, vha, 0x010c, in qla82xx_pinit_from_rom()
1201 for (i = 0; i < n; i++) { in qla82xx_pinit_from_rom()
1202 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || in qla82xx_pinit_from_rom()
1203 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { in qla82xx_pinit_from_rom()
1212 for (i = 0; i < n; i++) { in qla82xx_pinit_from_rom()
1223 if (off == QLA82XX_CAM_RAM(0x1fc)) in qla82xx_pinit_from_rom()
1227 if (off == (ROMUSB_GLB + 0xbc)) in qla82xx_pinit_from_rom()
1231 if (off == (ROMUSB_GLB + 0xc8)) in qla82xx_pinit_from_rom()
1241 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) in qla82xx_pinit_from_rom()
1244 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) in qla82xx_pinit_from_rom()
1248 ql_log(ql_log_fatal, vha, 0x0116, in qla82xx_pinit_from_rom()
1249 "Unknown addr: 0x%08lx.\n", buf[i].addr); in qla82xx_pinit_from_rom()
1256 * else crb_window returns 0xffffffff in qla82xx_pinit_from_rom()
1270 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); in qla82xx_pinit_from_rom()
1271 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); in qla82xx_pinit_from_rom()
1272 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); in qla82xx_pinit_from_rom()
1275 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); in qla82xx_pinit_from_rom()
1276 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); in qla82xx_pinit_from_rom()
1277 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); in qla82xx_pinit_from_rom()
1278 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); in qla82xx_pinit_from_rom()
1279 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); in qla82xx_pinit_from_rom()
1280 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); in qla82xx_pinit_from_rom()
1281 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); in qla82xx_pinit_from_rom()
1282 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); in qla82xx_pinit_from_rom()
1283 return 0; in qla82xx_pinit_from_rom()
1290 int i, j, ret = 0, loop, sz[2], off0; in qla82xx_pci_mem_write_2M()
1293 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; in qla82xx_pci_mem_write_2M()
1302 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) in qla82xx_pci_mem_write_2M()
1307 off0 = off & 0x7; in qla82xx_pci_mem_write_2M()
1308 sz[0] = (size < (8 - off0)) ? size : (8 - off0); in qla82xx_pci_mem_write_2M()
1309 sz[1] = size - sz[0]; in qla82xx_pci_mem_write_2M()
1311 off8 = off & 0xfffffff0; in qla82xx_pci_mem_write_2M()
1312 loop = (((off & 0xf) + size - 1) >> 4) + 1; in qla82xx_pci_mem_write_2M()
1315 startword = (off & 0xf)/8; in qla82xx_pci_mem_write_2M()
1317 for (i = 0; i < loop; i++) { in qla82xx_pci_mem_write_2M()
1339 if (sz[0] == 8) { in qla82xx_pci_mem_write_2M()
1343 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); in qla82xx_pci_mem_write_2M()
1346 if (sz[1] != 0) { in qla82xx_pci_mem_write_2M()
1347 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); in qla82xx_pci_mem_write_2M()
1348 word[startword+1] |= tmpw >> (sz[0] * 8); in qla82xx_pci_mem_write_2M()
1351 for (i = 0; i < loop; i++) { in qla82xx_pci_mem_write_2M()
1354 temp = 0; in qla82xx_pci_mem_write_2M()
1356 temp = word[i * scale] & 0xffffffff; in qla82xx_pci_mem_write_2M()
1358 temp = (word[i * scale] >> 32) & 0xffffffff; in qla82xx_pci_mem_write_2M()
1360 temp = word[i*scale + 1] & 0xffffffff; in qla82xx_pci_mem_write_2M()
1363 temp = (word[i*scale + 1] >> 32) & 0xffffffff; in qla82xx_pci_mem_write_2M()
1372 for (j = 0; j < MAX_CTL_CHECK; j++) { in qla82xx_pci_mem_write_2M()
1374 if ((temp & MIU_TA_CTL_BUSY) == 0) in qla82xx_pci_mem_write_2M()
1394 long size = 0; in qla82xx_fw_load_from_flash()
1402 for (i = 0; i < size; i++) { in qla82xx_fw_load_from_flash()
1412 if (i % 0x1000 == 0) in qla82xx_fw_load_from_flash()
1417 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); in qla82xx_fw_load_from_flash()
1418 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); in qla82xx_fw_load_from_flash()
1420 return 0; in qla82xx_fw_load_from_flash()
1427 int i, j = 0, k, start, end, loop, sz[2], off0[2]; in qla82xx_pci_mem_read_2M()
1430 uint64_t off8, val, mem_crb, word[2] = {0, 0}; in qla82xx_pci_mem_read_2M()
1440 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) in qla82xx_pci_mem_read_2M()
1445 off8 = off & 0xfffffff0; in qla82xx_pci_mem_read_2M()
1446 off0[0] = off & 0xf; in qla82xx_pci_mem_read_2M()
1447 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); in qla82xx_pci_mem_read_2M()
1449 loop = ((off0[0] + size - 1) >> shift_amount) + 1; in qla82xx_pci_mem_read_2M()
1450 off0[1] = 0; in qla82xx_pci_mem_read_2M()
1451 sz[1] = size - sz[0]; in qla82xx_pci_mem_read_2M()
1453 for (i = 0; i < loop; i++) { in qla82xx_pci_mem_read_2M()
1456 temp = 0; in qla82xx_pci_mem_read_2M()
1463 for (j = 0; j < MAX_CTL_CHECK; j++) { in qla82xx_pci_mem_read_2M()
1465 if ((temp & MIU_TA_CTL_BUSY) == 0) in qla82xx_pci_mem_read_2M()
1488 if ((off0[0] & 7) == 0) { in qla82xx_pci_mem_read_2M()
1489 val = word[0]; in qla82xx_pci_mem_read_2M()
1491 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | in qla82xx_pci_mem_read_2M()
1492 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); in qla82xx_pci_mem_read_2M()
1509 return 0; in qla82xx_pci_mem_read_2M()
1518 (struct qla82xx_uri_table_desc *)&unirom[0]; in qla82xx_get_table_desc()
1523 for (i = 0; i < entries; i++) { in qla82xx_get_table_desc()
1604 unsigned long val = 0; in qla82xx_pci_region_offset()
1608 case 0: in qla82xx_pci_region_offset()
1609 val = 0; in qla82xx_pci_region_offset()
1623 uint32_t len = 0; in qla82xx_iospace_config()
1626 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c, in qla82xx_iospace_config()
1632 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { in qla82xx_iospace_config()
1633 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d, in qla82xx_iospace_config()
1634 "Region #0 not an MMIO resource, aborting.\n"); in qla82xx_iospace_config()
1638 len = pci_resource_len(ha->pdev, 0); in qla82xx_iospace_config()
1639 ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len); in qla82xx_iospace_config()
1641 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, in qla82xx_iospace_config()
1650 ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11); in qla82xx_iospace_config()
1657 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, in qla82xx_iospace_config()
1675 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, in qla82xx_iospace_config()
1680 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, in qla82xx_iospace_config()
1685 return 0; in qla82xx_iospace_config()
1699 * Returns 0 on success.
1710 ql_dbg(ql_dbg_init, vha, 0x0043, in qla82xx_pci_config()
1713 return 0; in qla82xx_pci_config()
1720 * Returns 0 on success.
1737 struct req_que *req = ha->req_q_map[0]; in qla82xx_config_rings()
1738 struct rsp_que *rsp = ha->rsp_q_map[0]; in qla82xx_config_rings()
1742 icb->request_q_outpointer = cpu_to_le16(0); in qla82xx_config_rings()
1743 icb->response_q_inpointer = cpu_to_le16(0); in qla82xx_config_rings()
1749 wrt_reg_dword(®->req_q_out[0], 0); in qla82xx_config_rings()
1750 wrt_reg_dword(®->rsp_q_in[0], 0); in qla82xx_config_rings()
1751 wrt_reg_dword(®->rsp_q_out[0], 0); in qla82xx_config_rings()
1766 for (i = 0; i < size; i++) { in qla82xx_fw_load_from_blob()
1777 for (i = 0; i < size; i++) { in qla82xx_fw_load_from_blob()
1791 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC); in qla82xx_fw_load_from_blob()
1794 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); in qla82xx_fw_load_from_blob()
1795 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); in qla82xx_fw_load_from_blob()
1797 return 0; in qla82xx_fw_load_from_blob()
1810 int mn_present = 0; in qla82xx_set_product_offset()
1820 for (i = 0; i < entries; i++) { in qla82xx_set_product_offset()
1832 return 0; in qla82xx_set_product_offset()
1863 return 0; in qla82xx_validate_firmware_blob()
1869 u32 val = 0; in qla82xx_check_cmdpeg_state()
1887 ql_log(ql_log_info, vha, 0x00a8, in qla82xx_check_cmdpeg_state()
1888 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n", in qla82xx_check_cmdpeg_state()
1895 ql_log(ql_log_fatal, vha, 0x00a9, in qla82xx_check_cmdpeg_state()
1896 "Cmd Peg initialization failed: 0x%x.\n", val); in qla82xx_check_cmdpeg_state()
1908 u32 val = 0; in qla82xx_check_rcvpeg_state()
1926 ql_log(ql_log_info, vha, 0x00ab, in qla82xx_check_rcvpeg_state()
1927 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n", in qla82xx_check_rcvpeg_state()
1934 ql_log(ql_log_fatal, vha, 0x00ac, in qla82xx_check_rcvpeg_state()
1935 "Rcv Peg initialization failed: 0x%x.\n", val); in qla82xx_check_rcvpeg_state()
1963 ha->mailbox_out[0] = mb0; in qla82xx_mbx_completion()
1971 ql_dbg(ql_dbg_async, vha, 0x5053, in qla82xx_mbx_completion()
1991 int status = 0, status1 = 0; in qla82xx_intr_handler()
1994 uint32_t stat = 0; in qla82xx_intr_handler()
1999 ql_log(ql_log_info, NULL, 0xb053, in qla82xx_intr_handler()
2016 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); in qla82xx_intr_handler()
2031 switch (stat & 0xff) { in qla82xx_intr_handler()
2032 case 0x1: in qla82xx_intr_handler()
2033 case 0x2: in qla82xx_intr_handler()
2034 case 0x10: in qla82xx_intr_handler()
2035 case 0x11: in qla82xx_intr_handler()
2039 case 0x12: in qla82xx_intr_handler()
2040 mb[0] = MSW(stat); in qla82xx_intr_handler()
2046 case 0x13: in qla82xx_intr_handler()
2050 ql_dbg(ql_dbg_async, vha, 0x5054, in qla82xx_intr_handler()
2052 stat & 0xff); in qla82xx_intr_handler()
2056 wrt_reg_dword(®->host_int, 0); in qla82xx_intr_handler()
2063 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); in qla82xx_intr_handler()
2075 int status = 0; in qla82xx_msix_default()
2077 uint32_t stat = 0; in qla82xx_msix_default()
2078 uint32_t host_int = 0; in qla82xx_msix_default()
2100 switch (stat & 0xff) { in qla82xx_msix_default()
2101 case 0x1: in qla82xx_msix_default()
2102 case 0x2: in qla82xx_msix_default()
2103 case 0x10: in qla82xx_msix_default()
2104 case 0x11: in qla82xx_msix_default()
2108 case 0x12: in qla82xx_msix_default()
2109 mb[0] = MSW(stat); in qla82xx_msix_default()
2115 case 0x13: in qla82xx_msix_default()
2119 ql_dbg(ql_dbg_async, vha, 0x5041, in qla82xx_msix_default()
2121 stat & 0xff); in qla82xx_msix_default()
2125 wrt_reg_dword(®->host_int, 0); in qla82xx_msix_default()
2126 } while (0); in qla82xx_msix_default()
2142 uint32_t host_int = 0; in qla82xx_msix_rsp_q()
2159 wrt_reg_dword(®->host_int, 0); in qla82xx_msix_rsp_q()
2172 int status = 0; in qla82xx_poll()
2174 uint32_t host_int = 0; in qla82xx_poll()
2195 switch (stat & 0xff) { in qla82xx_poll()
2196 case 0x1: in qla82xx_poll()
2197 case 0x2: in qla82xx_poll()
2198 case 0x10: in qla82xx_poll()
2199 case 0x11: in qla82xx_poll()
2203 case 0x12: in qla82xx_poll()
2204 mb[0] = MSW(stat); in qla82xx_poll()
2210 case 0x13: in qla82xx_poll()
2214 ql_dbg(ql_dbg_p3p, vha, 0xb013, in qla82xx_poll()
2216 stat * 0xff); in qla82xx_poll()
2219 wrt_reg_dword(®->host_int, 0); in qla82xx_poll()
2233 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0); in qla82xx_enable_intrs()
2235 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); in qla82xx_enable_intrs()
2252 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); in qla82xx_disable_intrs()
2254 ha->interrupts_on = 0; in qla82xx_disable_intrs()
2285 ql_log(ql_log_info, vha, 0xb082, in qla82xx_set_idc_version()
2290 ql_log(ql_log_info, vha, 0xb083, in qla82xx_set_idc_version()
2306 if (drv_active == 0xffffffff) { in qla82xx_set_drv_active()
2349 if (drv_state == 0xffffffff) { in qla82xx_set_rst_ready()
2354 ql_dbg(ql_dbg_init, vha, 0x00bb, in qla82xx_set_rst_ready()
2355 "drv_state = 0x%08x.\n", drv_state); in qla82xx_set_rst_ready()
2398 ql_log(ql_log_fatal, vha, 0x009f, in qla82xx_load_fw()
2417 ql_log(ql_log_info, vha, 0x00a0, in qla82xx_load_fw()
2421 ql_log(ql_log_info, vha, 0x00a1, in qla82xx_load_fw()
2425 ql_log(ql_log_warn, vha, 0x0108, in qla82xx_load_fw()
2430 ql_log(ql_log_info, vha, 0x00a2, in qla82xx_load_fw()
2436 ql_log(ql_log_fatal, vha, 0x00a3, in qla82xx_load_fw()
2447 ql_log(ql_log_fatal, vha, 0x00a4, in qla82xx_load_fw()
2454 ql_log(ql_log_info, vha, 0x00a5, in qla82xx_load_fw()
2459 ql_log(ql_log_fatal, vha, 0x00a6, in qla82xx_load_fw()
2478 * of 0 before resetting the hardware in qla82xx_start_firmware()
2480 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); in qla82xx_start_firmware()
2481 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); in qla82xx_start_firmware()
2484 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); in qla82xx_start_firmware()
2485 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); in qla82xx_start_firmware()
2488 ql_log(ql_log_fatal, vha, 0x00a7, in qla82xx_start_firmware()
2495 ql_log(ql_log_fatal, vha, 0x00aa, in qla82xx_start_firmware()
2502 ha->link_width = (lnk >> 4) & 0x3f; in qla82xx_start_firmware()
2517 for (i = 0; i < length/4; i++, faddr += 4) { in qla82xx_read_flash_data()
2519 ql_log(ql_log_warn, vha, 0x0106, in qla82xx_read_flash_data()
2537 if (ret < 0) { in qla82xx_unprotect_flash()
2538 ql_log(ql_log_warn, vha, 0xb014, in qla82xx_unprotect_flash()
2544 if (ret < 0) in qla82xx_unprotect_flash()
2549 if (ret < 0) { in qla82xx_unprotect_flash()
2554 if (qla82xx_write_disable_flash(ha) != 0) in qla82xx_unprotect_flash()
2555 ql_log(ql_log_warn, vha, 0xb015, in qla82xx_unprotect_flash()
2571 if (ret < 0) { in qla82xx_protect_flash()
2572 ql_log(ql_log_warn, vha, 0xb016, in qla82xx_protect_flash()
2578 if (ret < 0) in qla82xx_protect_flash()
2584 if (ret < 0) in qla82xx_protect_flash()
2585 ql_log(ql_log_warn, vha, 0xb017, in qla82xx_protect_flash()
2588 if (qla82xx_write_disable_flash(ha) != 0) in qla82xx_protect_flash()
2589 ql_log(ql_log_warn, vha, 0xb018, in qla82xx_protect_flash()
2599 int ret = 0; in qla82xx_erase_sector()
2603 if (ret < 0) { in qla82xx_erase_sector()
2604 ql_log(ql_log_warn, vha, 0xb019, in qla82xx_erase_sector()
2615 ql_log(ql_log_warn, vha, 0xb01a, in qla82xx_erase_sector()
2648 int page_mode = 0; in qla82xx_write_flash_data()
2654 if (page_mode && !(faddr & 0xfff) && in qla82xx_write_flash_data()
2659 ql_log(ql_log_warn, vha, 0xb01b, in qla82xx_write_flash_data()
2670 ql_log(ql_log_warn, vha, 0xb01c, in qla82xx_write_flash_data()
2675 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { in qla82xx_write_flash_data()
2677 if ((faddr & rest_addr) == 0) { in qla82xx_write_flash_data()
2681 ql_log(ql_log_warn, vha, 0xb01d, in qla82xx_write_flash_data()
2697 ql_log(ql_log_warn, vha, 0xb01e, in qla82xx_write_flash_data()
2702 ql_log(ql_log_warn, vha, 0xb01f, in qla82xx_write_flash_data()
2719 ql_dbg(ql_dbg_p3p, vha, 0xb020, in qla82xx_write_flash_data()
2728 ql_log(ql_log_warn, vha, 0xb021, in qla82xx_write_flash_data()
2760 struct req_que *req = ha->req_q_map[0]; in qla82xx_start_iocbs()
2766 req->ring_index = 0; in qla82xx_start_iocbs()
2771 dbval = 0x04 | (ha->portnum << 5); in qla82xx_start_iocbs()
2790 uint32_t lock_owner = 0; in qla82xx_rom_lock_recovery()
2795 ql_log(ql_log_info, vha, 0xb022, in qla82xx_rom_lock_recovery()
2814 * Success : 0
2824 int need_reset = 0; in qla82xx_device_bootstrap()
2834 for (i = 0; i < 10; i++) { in qla82xx_device_bootstrap()
2846 ql_log(ql_log_info, vha, 0x009e, in qla82xx_device_bootstrap()
2855 ql_log(ql_log_fatal, vha, 0x00ad, in qla82xx_device_bootstrap()
2863 ql_log(ql_log_info, vha, 0x00ae, in qla82xx_device_bootstrap()
2901 drv_active = drv_active << 0x01; in qla82xx_need_qsnt_handler()
2909 ql_log(ql_log_info, vha, 0xb023, in qla82xx_need_qsnt_handler()
2915 ql_log(ql_log_info, vha, 0xb025, in qla82xx_need_qsnt_handler()
2931 drv_active = drv_active << 0x01; in qla82xx_need_qsnt_handler()
2936 ql_log(ql_log_info, vha, 0xb026, in qla82xx_need_qsnt_handler()
2974 ql_log(ql_log_fatal, vha, 0x00b8, in qla8xxx_dev_failed_handler()
2989 vha->flags.online = 0; in qla8xxx_dev_failed_handler()
2990 vha->flags.init_done = 0; in qla8xxx_dev_failed_handler()
3001 * Success : 0
3008 uint32_t active_mask = 0; in qla82xx_need_reset_handler()
3011 struct req_que *req = ha->req_q_map[0]; in qla82xx_need_reset_handler()
3023 ql_dbg(ql_dbg_p3p, vha, 0xb028, in qla82xx_need_reset_handler()
3024 "reset_acknowledged by 0x%x\n", ha->portnum); in qla82xx_need_reset_handler()
3029 ql_dbg(ql_dbg_p3p, vha, 0xb029, in qla82xx_need_reset_handler()
3030 "active_mask: 0x%08x\n", active_mask); in qla82xx_need_reset_handler()
3040 ql_dbg(ql_dbg_p3p, vha, 0xb02a, in qla82xx_need_reset_handler()
3041 "drv_state: 0x%08x, drv_active: 0x%08x, " in qla82xx_need_reset_handler()
3042 "dev_state: 0x%08x, active_mask: 0x%08x\n", in qla82xx_need_reset_handler()
3048 ql_log(ql_log_warn, vha, 0x00b5, in qla82xx_need_reset_handler()
3062 ql_dbg(ql_dbg_p3p, vha, 0xb02b, in qla82xx_need_reset_handler()
3063 "drv_state: 0x%08x, drv_active: 0x%08x, " in qla82xx_need_reset_handler()
3064 "dev_state: 0x%08x, active_mask: 0x%08x\n", in qla82xx_need_reset_handler()
3067 ql_log(ql_log_info, vha, 0x00b6, in qla82xx_need_reset_handler()
3068 "Device state is 0x%x = %s.\n", in qla82xx_need_reset_handler()
3075 ql_log(ql_log_info, vha, 0x00b7, in qla82xx_need_reset_handler()
3081 ql_log(ql_log_warn, vha, 0xb02c, in qla82xx_need_reset_handler()
3084 ql_log(ql_log_warn, vha, 0xb04f, in qla82xx_need_reset_handler()
3110 ql_dbg(ql_dbg_p3p, vha, 0xb02d, in qla82xx_check_md_needed()
3124 ql_log(ql_log_info, vha, 0xb02e, in qla82xx_check_md_needed()
3135 int status = 0; in qla82xx_check_fw_alive()
3139 /* all 0xff, assume AER/EEH in progress, ignore */ in qla82xx_check_fw_alive()
3140 if (fw_heartbeat_counter == 0xffffffff) { in qla82xx_check_fw_alive()
3141 ql_dbg(ql_dbg_timer, vha, 0x6003, in qla82xx_check_fw_alive()
3142 "FW heartbeat counter is 0xffffffff, " in qla82xx_check_fw_alive()
3150 vha->seconds_since_last_heartbeat = 0; in qla82xx_check_fw_alive()
3154 vha->seconds_since_last_heartbeat = 0; in qla82xx_check_fw_alive()
3157 ql_dbg(ql_dbg_timer, vha, 0x6004, in qla82xx_check_fw_alive()
3170 * Success : 0
3181 int loopcount = 0; in qla82xx_device_state_handler()
3191 ql_log(ql_log_info, vha, 0x009b, in qla82xx_device_state_handler()
3192 "Device state is 0x%x = %s.\n", in qla82xx_device_state_handler()
3202 ql_log(ql_log_fatal, vha, 0x009c, in qla82xx_device_state_handler()
3209 loopcount = 0; in qla82xx_device_state_handler()
3213 ql_log(ql_log_info, vha, 0x009d, in qla82xx_device_state_handler()
3214 "Device state is 0x%x = %s.\n", in qla82xx_device_state_handler()
3222 ha->flags.nic_core_reset_owner = 0; in qla82xx_device_state_handler()
3291 ql_log(ql_log_warn, vha, 0x600e, in qla82xx_check_temp()
3297 ql_log(ql_log_warn, vha, 0x600f, in qla82xx_check_temp()
3302 return 0; in qla82xx_check_temp()
3319 ha->flags.mbox_busy = 0; in qla82xx_clear_pending_mbx()
3320 ql_log(ql_log_warn, vha, 0x6010, in qla82xx_clear_pending_mbx()
3341 ql_log(ql_log_warn, vha, 0x6001, in qla82xx_watchdog()
3346 ql_log(ql_log_warn, vha, 0x6002, in qla82xx_watchdog()
3352 ql_log(ql_log_warn, vha, 0xb055, in qla82xx_watchdog()
3359 ql_dbg(ql_dbg_timer, vha, 0x6011, in qla82xx_watchdog()
3360 "disabling pause transmit on port 0 & 1.\n"); in qla82xx_watchdog()
3361 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98, in qla82xx_watchdog()
3365 ql_log(ql_log_info, vha, 0x6005, in qla82xx_watchdog()
3367 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n " in qla82xx_watchdog()
3368 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n " in qla82xx_watchdog()
3369 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n " in qla82xx_watchdog()
3370 " PEG_NET_4_PC: 0x%x.\n", halt_status, in qla82xx_watchdog()
3373 QLA82XX_CRB_PEG_NET_0 + 0x3c), in qla82xx_watchdog()
3375 QLA82XX_CRB_PEG_NET_1 + 0x3c), in qla82xx_watchdog()
3377 QLA82XX_CRB_PEG_NET_2 + 0x3c), in qla82xx_watchdog()
3379 QLA82XX_CRB_PEG_NET_3 + 0x3c), in qla82xx_watchdog()
3381 QLA82XX_CRB_PEG_NET_4 + 0x3c)); in qla82xx_watchdog()
3382 if (((halt_status & 0x1fffff00) >> 8) == 0x67) in qla82xx_watchdog()
3383 ql_log(ql_log_warn, vha, 0xb052, in qla82xx_watchdog()
3385 "error code 0x00006700. Device is " in qla82xx_watchdog()
3391 ql_log(ql_log_info, vha, 0x6006, in qla82xx_watchdog()
3397 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n"); in qla82xx_watchdog()
3425 uint32_t dev_state = 0; in qla82xx_set_reset_owner()
3433 ql_log(ql_log_info, vha, 0xb02f, in qla82xx_set_reset_owner()
3439 ql_dbg(ql_dbg_p3p, vha, 0xb030, in qla82xx_set_reset_owner()
3440 "reset_owner is 0x%x\n", ha->portnum); in qla82xx_set_reset_owner()
3445 ql_log(ql_log_info, vha, 0xb031, in qla82xx_set_reset_owner()
3446 "Device state is 0x%x = %s.\n", in qla82xx_set_reset_owner()
3459 * 0 = success
3468 ql_log(ql_log_warn, vha, 0x8024, in qla82xx_abort_isp()
3493 ha->flags.isp82xx_fw_hung = 0; in qla82xx_abort_isp()
3494 ha->flags.nic_core_reset_hdlr_active = 0; in qla82xx_abort_isp()
3501 if (ha->isp_abort_cnt == 0) { in qla82xx_abort_isp()
3502 ql_log(ql_log_warn, vha, 0x8027, in qla82xx_abort_isp()
3510 vha->flags.online = 0; in qla82xx_abort_isp()
3516 ql_log(ql_log_warn, vha, 0x8036, in qla82xx_abort_isp()
3523 ql_dbg(ql_dbg_taskm, vha, 0x8029, in qla82xx_abort_isp()
3544 * 0 = success
3575 * Success (fcoe_ctx reset is done) : 0
3597 ql_dbg(ql_dbg_p3p, vha, 0xb027, in qla2x00_wait_for_fcoe_ctx_reset()
3606 int i, fw_state = 0; in qla82xx_chip_reset_cleanup()
3615 for (i = 0; i < 2; i++) { in qla82xx_chip_reset_cleanup()
3628 ql_dbg(ql_dbg_init, vha, 0x00b0, in qla82xx_chip_reset_cleanup()
3639 for (que = 0; que < ha->max_req_queues; que++) { in qla82xx_chip_reset_cleanup()
3654 0x00b1, in qla82xx_chip_reset_cleanup()
3658 0x00b2, in qla82xx_chip_reset_cleanup()
3669 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, in qla82xx_chip_reset_cleanup()
3671 ql_dbg(ql_dbg_init, vha, 0x00b3, in qla82xx_chip_reset_cleanup()
3698 for (i = 0; i < crb_entry->op_count; i++) { in qla82xx_minidump_process_control()
3707 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); in qla82xx_minidump_process_control()
3713 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); in qla82xx_minidump_process_control()
3724 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); in qla82xx_minidump_process_control()
3733 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0); in qla82xx_minidump_process_control()
3745 crb_addr, 0, 0); in qla82xx_minidump_process_control()
3757 read_value = qla82xx_md_rw_32(ha, addr, 0, 0); in qla82xx_minidump_process_control()
3812 for (i = 0; i < loop_cnt; i++) { in qla82xx_minidump_process_rdocm()
3836 for (i = 0; i < loop_cnt; i++) { in qla82xx_minidump_process_rdmux()
3838 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); in qla82xx_minidump_process_rdmux()
3860 for (i = 0; i < loop_cnt; i++) { in qla82xx_minidump_process_rdcrb()
3861 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); in qla82xx_minidump_process_rdcrb()
3894 for (i = 0; i < loop_count; i++) { in qla82xx_minidump_process_l2tag()
3902 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0); in qla82xx_minidump_process_l2tag()
3903 if ((c_value_r & p_mask) == 0) in qla82xx_minidump_process_l2tag()
3907 ql_dbg(ql_dbg_p3p, vha, 0xb032, in qla82xx_minidump_process_l2tag()
3908 "c_value_r: 0x%x, poll_mask: 0x%lx, " in qla82xx_minidump_process_l2tag()
3909 "w_time: 0x%lx\n", in qla82xx_minidump_process_l2tag()
3917 for (k = 0; k < r_cnt; k++) { in qla82xx_minidump_process_l2tag()
3918 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); in qla82xx_minidump_process_l2tag()
3949 for (i = 0; i < loop_count; i++) { in qla82xx_minidump_process_l1cache()
3953 for (k = 0; k < r_cnt; k++) { in qla82xx_minidump_process_l1cache()
3954 r_value = qla82xx_md_rw_32(ha, addr, 0, 0); in qla82xx_minidump_process_l1cache()
3969 uint32_t r_stride, r_value, r_cnt, qid = 0; in qla82xx_minidump_process_queue()
3980 for (i = 0; i < loop_cnt; i++) { in qla82xx_minidump_process_queue()
3983 for (k = 0; k < r_cnt; k++) { in qla82xx_minidump_process_queue()
3984 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0); in qla82xx_minidump_process_queue()
4007 for (i = 0; i < loop_cnt; i++) { in qla82xx_minidump_process_rdrom()
4009 (r_addr & 0xFFFF0000), 1); in qla82xx_minidump_process_rdrom()
4012 (r_addr & 0x0000FFFF), 0, 0); in qla82xx_minidump_process_rdrom()
4035 if (r_addr & 0xf) { in qla82xx_minidump_process_rdmem()
4036 ql_log(ql_log_warn, vha, 0xb033, in qla82xx_minidump_process_rdmem()
4037 "Read addr 0x%x not 16 bytes aligned\n", r_addr); in qla82xx_minidump_process_rdmem()
4042 ql_log(ql_log_warn, vha, 0xb034, in qla82xx_minidump_process_rdmem()
4043 "Read data[0x%x] not multiple of 16 bytes\n", in qla82xx_minidump_process_rdmem()
4048 ql_dbg(ql_dbg_p3p, vha, 0xb035, in qla82xx_minidump_process_rdmem()
4049 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", in qla82xx_minidump_process_rdmem()
4053 for (i = 0; i < loop_cnt; i++) { in qla82xx_minidump_process_rdmem()
4055 r_value = 0; in qla82xx_minidump_process_rdmem()
4062 for (j = 0; j < MAX_CTL_CHECK; j++) { in qla82xx_minidump_process_rdmem()
4064 MD_MIU_TEST_AGT_CTRL, 0, 0); in qla82xx_minidump_process_rdmem()
4065 if ((r_value & MIU_TA_CTL_BUSY) == 0) in qla82xx_minidump_process_rdmem()
4076 for (j = 0; j < 4; j++) { in qla82xx_minidump_process_rdmem()
4078 MD_MIU_TEST_AGT_RDDATA[j], 0, 0); in qla82xx_minidump_process_rdmem()
4092 uint64_t chksum = 0; in qla82xx_validate_template_chksum()
4096 while (count-- > 0) in qla82xx_validate_template_chksum()
4099 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32); in qla82xx_validate_template_chksum()
4108 ql_dbg(ql_dbg_p3p, vha, 0xb036, in qla82xx_mark_entry_skipped()
4110 "ETYPE[0x%x]-ELEVEL[0x%x]\n", in qla82xx_mark_entry_skipped()
4119 int no_entry_hdr = 0; in qla82xx_md_collect()
4123 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0; in qla82xx_md_collect()
4124 int i = 0, rval = QLA_FUNCTION_FAILED; in qla82xx_md_collect()
4130 ql_log(ql_log_warn, vha, 0xb037, in qla82xx_md_collect()
4139 ql_log(ql_log_warn, vha, 0xb038, in qla82xx_md_collect()
4145 ql_log(ql_log_warn, vha, 0xb054, in qla82xx_md_collect()
4148 ha->flags.isp82xx_no_md_cap = 0; in qla82xx_md_collect()
4153 ql_log(ql_log_info, vha, 0xb039, in qla82xx_md_collect()
4159 ql_dbg(ql_dbg_p3p, vha, 0xb03a, in qla82xx_md_collect()
4160 "No of entry headers in Template: 0x%x\n", no_entry_hdr); in qla82xx_md_collect()
4162 ql_dbg(ql_dbg_p3p, vha, 0xb03b, in qla82xx_md_collect()
4163 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); in qla82xx_md_collect()
4165 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; in qla82xx_md_collect()
4168 if ((f_capture_mask & 0x3) != 0x3) { in qla82xx_md_collect()
4169 ql_log(ql_log_warn, vha, 0xb03c, in qla82xx_md_collect()
4170 "Minimum required capture mask[0x%x] level not set\n", in qla82xx_md_collect()
4176 tmplt_hdr->driver_info[0] = vha->host_no; in qla82xx_md_collect()
4183 ql_dbg(ql_dbg_p3p, vha, 0xb03d, in qla82xx_md_collect()
4184 "Total minidump data_size 0x%x to be captured\n", total_data_size); in qla82xx_md_collect()
4188 ql_log(ql_log_warn, vha, 0xb04e, in qla82xx_md_collect()
4189 "Bad template header entry type: 0x%x obtained\n", in qla82xx_md_collect()
4198 for (i = 0; i < no_entry_hdr; i++) { in qla82xx_md_collect()
4201 ql_log(ql_log_warn, vha, 0xb03e, in qla82xx_md_collect()
4202 "More MiniDump data collected: [0x%x]\n", in qla82xx_md_collect()
4211 ql_dbg(ql_dbg_p3p, vha, 0xb03f, in qla82xx_md_collect()
4213 "ETYPE[0x%x]-ELEVEL[0x%x]\n", in qla82xx_md_collect()
4219 ql_dbg(ql_dbg_p3p, vha, 0xb040, in qla82xx_md_collect()
4221 "entry_type: 0x%x, capture_mask: 0x%x\n", in qla82xx_md_collect()
4226 ql_dbg(ql_dbg_p3p, vha, 0xb041, in qla82xx_md_collect()
4227 "Data collected: [0x%x], Dump size left:[0x%x]\n", in qla82xx_md_collect()
4295 ql_dbg(ql_dbg_p3p, vha, 0xb042, in qla82xx_md_collect()
4306 ql_dbg(ql_dbg_p3p, vha, 0xb043, in qla82xx_md_collect()
4307 "MiniDump data mismatch: Data collected: [0x%x]," in qla82xx_md_collect()
4308 "total_data_size:[0x%x]\n", in qla82xx_md_collect()
4313 ql_log(ql_log_info, vha, 0xb044, in qla82xx_md_collect()
4332 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) { in qla82xx_md_alloc()
4333 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF; in qla82xx_md_alloc()
4334 ql_log(ql_log_info, vha, 0xb045, in qla82xx_md_alloc()
4335 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n", in qla82xx_md_alloc()
4339 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) { in qla82xx_md_alloc()
4345 ql_log(ql_log_warn, vha, 0xb046, in qla82xx_md_alloc()
4352 ql_log(ql_log_warn, vha, 0xb047, in qla82xx_md_alloc()
4354 "(0x%x).\n", ha->md_dump_size); in qla82xx_md_alloc()
4357 return 0; in qla82xx_md_alloc()
4367 ql_log(ql_log_info, vha, 0xb048, in qla82xx_md_free()
4377 ql_log(ql_log_info, vha, 0xb049, in qla82xx_md_free()
4381 ha->md_dump_size = 0; in qla82xx_md_free()
4395 ql_log(ql_log_info, vha, 0xb04a, in qla82xx_md_prep()
4406 ql_dbg(ql_dbg_p3p, vha, 0xb04b, in qla82xx_md_prep()
4412 ql_log(ql_log_info, vha, 0xb04c, in qla82xx_md_prep()
4416 ql_log(ql_log_info, vha, 0xb04d, in qla82xx_md_prep()
4441 ql_log(ql_log_warn, vha, 0xb050, in qla82xx_beacon_on()
4459 rval = qla82xx_mbx_beacon_ctl(vha, 0); in qla82xx_beacon_off()
4462 ql_log(ql_log_warn, vha, 0xb051, in qla82xx_beacon_off()
4466 ha->beacon_blink_led = 0; in qla82xx_beacon_off()