Lines Matching refs:RD_REG_WORD
739 ha->mailbox_out[0] = RD_REG_WORD(®->mailbox0); in qla1280_mailbox_timeout()
742 RD_REG_WORD(®->ictrl), RD_REG_WORD(®->istatus)); in qla1280_mailbox_timeout()
840 RD_REG_WORD(&ha->iobase->istatus)); in qla1280_error_action()
843 RD_REG_WORD(&ha->iobase->host_cmd), in qla1280_error_action()
844 RD_REG_WORD(&ha->iobase->ictrl), jiffies); in qla1280_error_action()
1063 RD_REG_WORD(&ha->iobase->ictrl); /* PCI Posted Write flush */ in qla1280_disable_intrs()
1071 RD_REG_WORD(&ha->iobase->ictrl); /* PCI Posted Write flush */ in qla1280_enable_intrs()
1432 RD_REG_WORD(®->host_cmd); in qla1280_initialize_adapter()
1581 data = RD_REG_WORD(®->ictrl); in qla1280_chip_diag()
1597 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_chip_diag()
1605 data = RD_REG_WORD(®->mailbox0); in qla1280_chip_diag()
1614 if (RD_REG_WORD(®->mailbox1) != PROD_ID_1 || in qla1280_chip_diag()
1615 (RD_REG_WORD(®->mailbox2) != PROD_ID_2 && in qla1280_chip_diag()
1616 RD_REG_WORD(®->mailbox2) != PROD_ID_2a) || in qla1280_chip_diag()
1617 RD_REG_WORD(®->mailbox3) != PROD_ID_3 || in qla1280_chip_diag()
1618 RD_REG_WORD(®->mailbox4) != PROD_ID_4) { in qla1280_chip_diag()
1621 RD_REG_WORD(®->mailbox1), in qla1280_chip_diag()
1622 RD_REG_WORD(®->mailbox2), in qla1280_chip_diag()
1623 RD_REG_WORD(®->mailbox3), in qla1280_chip_diag()
1624 RD_REG_WORD(®->mailbox4)); in qla1280_chip_diag()
2189 hwrev = RD_REG_WORD(®->cfg_0) & ISP_CFG0_HWMSK; in qla1280_nvram_config()
2191 cfg1 = RD_REG_WORD(®->cfg_1) & ~(BIT_4 | BIT_5 | BIT_6); in qla1280_nvram_config()
2192 cdma_conf = RD_REG_WORD(®->cdma_cfg); in qla1280_nvram_config()
2220 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nvram_config()
2223 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nvram_config()
2369 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nvram_request()
2372 reg_data = RD_REG_WORD(®->nvram); in qla1280_nvram_request()
2376 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nvram_request()
2383 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nvram_request()
2395 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nv_write()
2398 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nv_write()
2401 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nv_write()
2476 mb[0], ha->mailbox_out[0], RD_REG_WORD(®->istatus)); in qla1280_mailbox_command()
2478 RD_REG_WORD(®->mailbox0), RD_REG_WORD(®->mailbox1), in qla1280_mailbox_command()
2479 RD_REG_WORD(®->mailbox2), RD_REG_WORD(®->mailbox3)); in qla1280_mailbox_command()
2481 RD_REG_WORD(®->mailbox4), RD_REG_WORD(®->mailbox5), in qla1280_mailbox_command()
2482 RD_REG_WORD(®->mailbox6), RD_REG_WORD(®->mailbox7)); in qla1280_mailbox_command()
2520 data = RD_REG_WORD(®->istatus); in qla1280_poll()
2690 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_reset_adapter()
2774 cnt = RD_REG_WORD(®->mailbox4); in qla1280_64bit_start_scsi()
3036 cnt = RD_REG_WORD(®->mailbox4); in qla1280_32bit_start_scsi()
3253 cnt = RD_REG_WORD(®->mailbox4); in qla1280_req_pkt()
3356 istatus = RD_REG_WORD(®->istatus); in qla1280_isr()
3361 mailbox[5] = RD_REG_WORD(®->mailbox5); in qla1280_isr()
3372 *wptr++ = RD_REG_WORD(®->mailbox0); in qla1280_isr()
3373 *wptr++ = RD_REG_WORD(®->mailbox1); in qla1280_isr()
3374 *wptr = RD_REG_WORD(®->mailbox2); in qla1280_isr()
3377 *wptr++ = RD_REG_WORD(®->mailbox3); in qla1280_isr()
3378 *wptr++ = RD_REG_WORD(®->mailbox4); in qla1280_isr()
3380 *wptr++ = RD_REG_WORD(®->mailbox6); in qla1280_isr()
3381 *wptr = RD_REG_WORD(®->mailbox7); in qla1280_isr()
3776 RD_REG_WORD(®->id_l); in qla1280_abort_isp()
3840 ret = RD_REG_WORD(addr); in qla1280_debounce_register()
3841 ret2 = RD_REG_WORD(addr); in qla1280_debounce_register()
3848 ret = RD_REG_WORD(addr); in qla1280_debounce_register()
3849 ret2 = RD_REG_WORD(addr); in qla1280_debounce_register()
3871 config_reg = RD_REG_WORD(®->cfg_1); in qla1280_check_for_dead_scsi_bus()
3873 scsi_control = RD_REG_WORD(®->scsiControlPins); in qla1280_check_for_dead_scsi_bus()