54 	pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);  in pm80xx_bar4_shift()
134 		pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,  in pm80xx_get_fatal_dump()
273 		pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,  in pm80xx_get_fatal_dump()
350 				pm8001_cw32(pm8001_ha, 0,  in pm80xx_get_fatal_dump()
454 	pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET,  in pm80xx_get_non_fatal_dump()
994 	pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);  in mpi_init_check()
1497 	pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);  in mpi_uninit_check()
1573 	pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);  in pm80xx_chip_soft_rst()
1650 	pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);  in pm80xx_hw_chip_rst()
1673 	pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);  in pm80xx_chip_intx_interrupt_enable()
1674 	pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);  in pm80xx_chip_intx_interrupt_enable()
1684 	pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);  in pm80xx_chip_intx_interrupt_disable()
1697 		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec);  in pm80xx_chip_interrupt_enable()
1699 		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U,  in pm80xx_chip_interrupt_enable()
1718 		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF);  in pm80xx_chip_interrupt_disable()
1719 		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF);  in pm80xx_chip_interrupt_disable()
1721 		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec);  in pm80xx_chip_interrupt_disable()
1723 		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U,  in pm80xx_chip_interrupt_disable()