Lines Matching refs:pm8001_ha
50 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha) in read_main_config_table() argument
52 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; in read_main_config_table()
53 pm8001_ha->main_cfg_tbl.pm8001_tbl.signature = in read_main_config_table()
55 pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev = in read_main_config_table()
57 pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev = in read_main_config_table()
59 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io = in read_main_config_table()
61 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl = in read_main_config_table()
63 pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag = in read_main_config_table()
65 pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset = in read_main_config_table()
67 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset = in read_main_config_table()
69 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset = in read_main_config_table()
71 pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag = in read_main_config_table()
75 pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset = in read_main_config_table()
79 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 = in read_main_config_table()
81 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 = in read_main_config_table()
83 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 = in read_main_config_table()
85 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 = in read_main_config_table()
93 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha) in read_general_status_table() argument
95 void __iomem *address = pm8001_ha->general_stat_tbl_addr; in read_general_status_table()
96 pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate = in read_general_status_table()
98 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0 = in read_general_status_table()
100 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1 = in read_general_status_table()
102 pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt = in read_general_status_table()
104 pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt = in read_general_status_table()
106 pm8001_ha->gs_tbl.pm8001_tbl.rsvd = in read_general_status_table()
108 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0] = in read_general_status_table()
110 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1] = in read_general_status_table()
112 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2] = in read_general_status_table()
114 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3] = in read_general_status_table()
116 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4] = in read_general_status_table()
118 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5] = in read_general_status_table()
120 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6] = in read_general_status_table()
122 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7] = in read_general_status_table()
124 pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val = in read_general_status_table()
126 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0] = in read_general_status_table()
128 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1] = in read_general_status_table()
130 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0] = in read_general_status_table()
132 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1] = in read_general_status_table()
134 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2] = in read_general_status_table()
136 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3] = in read_general_status_table()
138 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4] = in read_general_status_table()
140 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5] = in read_general_status_table()
142 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6] = in read_general_status_table()
144 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7] = in read_general_status_table()
152 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha) in read_inbnd_queue_table() argument
155 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; in read_inbnd_queue_table()
158 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = in read_inbnd_queue_table()
160 pm8001_ha->inbnd_q_tbl[i].pi_offset = in read_inbnd_queue_table()
169 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha) in read_outbnd_queue_table() argument
172 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; in read_outbnd_queue_table()
175 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = in read_outbnd_queue_table()
177 pm8001_ha->outbnd_q_tbl[i].ci_offset = in read_outbnd_queue_table()
186 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) in init_default_table_values() argument
190 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; in init_default_table_values()
191 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; in init_default_table_values()
192 u32 ib_offset = pm8001_ha->ib_offset; in init_default_table_values()
193 u32 ob_offset = pm8001_ha->ob_offset; in init_default_table_values()
194 u32 ci_offset = pm8001_ha->ci_offset; in init_default_table_values()
195 u32 pi_offset = pm8001_ha->pi_offset; in init_default_table_values()
197 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd = 0; in init_default_table_values()
198 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3 = 0; in init_default_table_values()
199 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7 = 0; in init_default_table_values()
200 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3 = 0; in init_default_table_values()
201 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7 = 0; in init_default_table_values()
202 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 = in init_default_table_values()
204 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 = in init_default_table_values()
206 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0; in init_default_table_values()
207 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0; in init_default_table_values()
208 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0; in init_default_table_values()
209 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0; in init_default_table_values()
211 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr = in init_default_table_values()
212 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; in init_default_table_values()
213 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr = in init_default_table_values()
214 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; in init_default_table_values()
215 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size = in init_default_table_values()
217 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option = 0x01; in init_default_table_values()
218 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr = in init_default_table_values()
219 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; in init_default_table_values()
220 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr = in init_default_table_values()
221 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; in init_default_table_values()
222 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size = in init_default_table_values()
224 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option = 0x01; in init_default_table_values()
225 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt = 0x01; in init_default_table_values()
226 for (i = 0; i < pm8001_ha->max_q_num; i++) { in init_default_table_values()
227 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = in init_default_table_values()
228 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); in init_default_table_values()
229 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = in init_default_table_values()
230 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi; in init_default_table_values()
231 pm8001_ha->inbnd_q_tbl[i].lower_base_addr = in init_default_table_values()
232 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo; in init_default_table_values()
233 pm8001_ha->inbnd_q_tbl[i].base_virt = in init_default_table_values()
234 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr; in init_default_table_values()
235 pm8001_ha->inbnd_q_tbl[i].total_length = in init_default_table_values()
236 pm8001_ha->memoryMap.region[ib_offset + i].total_len; in init_default_table_values()
237 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = in init_default_table_values()
238 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi; in init_default_table_values()
239 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = in init_default_table_values()
240 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo; in init_default_table_values()
241 pm8001_ha->inbnd_q_tbl[i].ci_virt = in init_default_table_values()
242 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr; in init_default_table_values()
244 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = in init_default_table_values()
247 pm8001_ha->inbnd_q_tbl[i].pi_offset = in init_default_table_values()
249 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; in init_default_table_values()
250 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; in init_default_table_values()
252 for (i = 0; i < pm8001_ha->max_q_num; i++) { in init_default_table_values()
253 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = in init_default_table_values()
254 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); in init_default_table_values()
255 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = in init_default_table_values()
256 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi; in init_default_table_values()
257 pm8001_ha->outbnd_q_tbl[i].lower_base_addr = in init_default_table_values()
258 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo; in init_default_table_values()
259 pm8001_ha->outbnd_q_tbl[i].base_virt = in init_default_table_values()
260 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr; in init_default_table_values()
261 pm8001_ha->outbnd_q_tbl[i].total_length = in init_default_table_values()
262 pm8001_ha->memoryMap.region[ob_offset + i].total_len; in init_default_table_values()
263 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = in init_default_table_values()
264 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi; in init_default_table_values()
265 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = in init_default_table_values()
266 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo; in init_default_table_values()
267 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = in init_default_table_values()
269 pm8001_ha->outbnd_q_tbl[i].pi_virt = in init_default_table_values()
270 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr; in init_default_table_values()
272 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = in init_default_table_values()
275 pm8001_ha->outbnd_q_tbl[i].ci_offset = in init_default_table_values()
277 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; in init_default_table_values()
278 pm8001_ha->outbnd_q_tbl[i].producer_index = 0; in init_default_table_values()
286 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha) in update_main_config_table() argument
288 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; in update_main_config_table()
290 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd); in update_main_config_table()
292 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3); in update_main_config_table()
294 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7); in update_main_config_table()
296 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3); in update_main_config_table()
298 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7); in update_main_config_table()
300 pm8001_ha->main_cfg_tbl.pm8001_tbl. in update_main_config_table()
303 pm8001_ha->main_cfg_tbl.pm8001_tbl. in update_main_config_table()
306 pm8001_ha->main_cfg_tbl.pm8001_tbl. in update_main_config_table()
309 pm8001_ha->main_cfg_tbl.pm8001_tbl. in update_main_config_table()
312 pm8001_ha->main_cfg_tbl.pm8001_tbl. in update_main_config_table()
315 pm8001_ha->main_cfg_tbl.pm8001_tbl. in update_main_config_table()
318 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr); in update_main_config_table()
320 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr); in update_main_config_table()
322 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size); in update_main_config_table()
324 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option); in update_main_config_table()
326 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr); in update_main_config_table()
328 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr); in update_main_config_table()
330 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size); in update_main_config_table()
332 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option); in update_main_config_table()
334 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt); in update_main_config_table()
342 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, in update_inbnd_queue_table() argument
345 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; in update_inbnd_queue_table()
348 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); in update_inbnd_queue_table()
350 pm8001_ha->inbnd_q_tbl[number].upper_base_addr); in update_inbnd_queue_table()
352 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); in update_inbnd_queue_table()
354 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); in update_inbnd_queue_table()
356 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); in update_inbnd_queue_table()
364 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, in update_outbnd_queue_table() argument
367 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; in update_outbnd_queue_table()
370 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); in update_outbnd_queue_table()
372 pm8001_ha->outbnd_q_tbl[number].upper_base_addr); in update_outbnd_queue_table()
374 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); in update_outbnd_queue_table()
376 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); in update_outbnd_queue_table()
378 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); in update_outbnd_queue_table()
380 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); in update_outbnd_queue_table()
388 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue) in pm8001_bar4_shift() argument
394 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue); in pm8001_bar4_shift()
399 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW); in pm8001_bar4_shift()
403 pm8001_dbg(pm8001_ha, INIT, in pm8001_bar4_shift()
416 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, in mpi_set_phys_g3_with_ssc() argument
434 spin_lock_irqsave(&pm8001_ha->lock, flags); in mpi_set_phys_g3_with_ssc()
435 if (-1 == pm8001_bar4_shift(pm8001_ha, in mpi_set_phys_g3_with_ssc()
437 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in mpi_set_phys_g3_with_ssc()
443 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); in mpi_set_phys_g3_with_ssc()
446 if (-1 == pm8001_bar4_shift(pm8001_ha, in mpi_set_phys_g3_with_ssc()
448 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in mpi_set_phys_g3_with_ssc()
453 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501); in mpi_set_phys_g3_with_ssc()
470 value = pm8001_cr32(pm8001_ha, 2, 0xd8); in mpi_set_phys_g3_with_ssc()
471 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016); in mpi_set_phys_g3_with_ssc()
474 pm8001_bar4_shift(pm8001_ha, 0x0); in mpi_set_phys_g3_with_ssc()
475 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in mpi_set_phys_g3_with_ssc()
484 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha, in mpi_set_open_retry_interval_reg() argument
499 spin_lock_irqsave(&pm8001_ha->lock, flags); in mpi_set_open_retry_interval_reg()
501 if (-1 == pm8001_bar4_shift(pm8001_ha, in mpi_set_open_retry_interval_reg()
503 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in mpi_set_open_retry_interval_reg()
508 pm8001_cw32(pm8001_ha, 2, offset, value); in mpi_set_open_retry_interval_reg()
511 if (-1 == pm8001_bar4_shift(pm8001_ha, in mpi_set_open_retry_interval_reg()
513 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in mpi_set_open_retry_interval_reg()
518 pm8001_cw32(pm8001_ha, 2, offset, value); in mpi_set_open_retry_interval_reg()
521 pm8001_bar4_shift(pm8001_ha, 0x0); in mpi_set_open_retry_interval_reg()
522 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in mpi_set_open_retry_interval_reg()
530 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) in mpi_init_check() argument
537 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE); in mpi_init_check()
542 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); in mpi_init_check()
550 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, in mpi_init_check()
565 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha) in check_fw_ready() argument
570 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); in check_fw_ready()
571 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); in check_fw_ready()
575 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); in check_fw_ready()
582 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); in check_fw_ready()
590 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); in check_fw_ready()
606 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) in check_fw_ready()
608 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) in check_fw_ready()
616 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha) in init_pci_device_addresses() argument
624 value = pm8001_cr32(pm8001_ha, 0, 0x44); in init_pci_device_addresses()
626 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 Offset: %x\n", offset); in init_pci_device_addresses()
629 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar); in init_pci_device_addresses()
630 pm8001_ha->main_cfg_tbl_addr = base_addr = in init_pci_device_addresses()
631 pm8001_ha->io_mem[pcibar].memvirtaddr + offset; in init_pci_device_addresses()
632 pm8001_ha->general_stat_tbl_addr = in init_pci_device_addresses()
633 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18); in init_pci_device_addresses()
634 pm8001_ha->inbnd_q_tbl_addr = in init_pci_device_addresses()
635 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C); in init_pci_device_addresses()
636 pm8001_ha->outbnd_q_tbl_addr = in init_pci_device_addresses()
637 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20); in init_pci_device_addresses()
644 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha) in pm8001_chip_init() argument
648 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); in pm8001_chip_init()
652 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) { in pm8001_chip_init()
653 pm8001_dbg(pm8001_ha, FAIL, in pm8001_chip_init()
660 if (-1 == check_fw_ready(pm8001_ha)) { in pm8001_chip_init()
661 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n"); in pm8001_chip_init()
666 init_pci_device_addresses(pm8001_ha); in pm8001_chip_init()
667 init_default_table_values(pm8001_ha); in pm8001_chip_init()
668 read_main_config_table(pm8001_ha); in pm8001_chip_init()
669 read_general_status_table(pm8001_ha); in pm8001_chip_init()
670 read_inbnd_queue_table(pm8001_ha); in pm8001_chip_init()
671 read_outbnd_queue_table(pm8001_ha); in pm8001_chip_init()
673 update_main_config_table(pm8001_ha); in pm8001_chip_init()
674 for (i = 0; i < pm8001_ha->max_q_num; i++) in pm8001_chip_init()
675 update_inbnd_queue_table(pm8001_ha, i); in pm8001_chip_init()
676 for (i = 0; i < pm8001_ha->max_q_num; i++) in pm8001_chip_init()
677 update_outbnd_queue_table(pm8001_ha, i); in pm8001_chip_init()
680 mpi_set_phys_g3_with_ssc(pm8001_ha, 0); in pm8001_chip_init()
682 mpi_set_open_retry_interval_reg(pm8001_ha, 119); in pm8001_chip_init()
685 if (0 == mpi_init_check(pm8001_ha)) { in pm8001_chip_init()
686 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n"); in pm8001_chip_init()
694 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1); in pm8001_chip_init()
695 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0); in pm8001_chip_init()
699 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha) in mpi_uninit_check() argument
705 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid); in mpi_uninit_check()
707 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) { in mpi_uninit_check()
708 pm8001_dbg(pm8001_ha, FAIL, in mpi_uninit_check()
714 init_pci_device_addresses(pm8001_ha); in mpi_uninit_check()
717 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET); in mpi_uninit_check()
723 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); in mpi_uninit_check()
728 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=0x%x\n", in mpi_uninit_check()
739 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, in mpi_uninit_check()
746 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n", in mpi_uninit_check()
757 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha) in soft_reset_ready_check() argument
760 if (mpi_uninit_check(pm8001_ha) != 0) { in soft_reset_ready_check()
761 pm8001_dbg(pm8001_ha, FAIL, "MPI state is not ready\n"); in soft_reset_ready_check()
765 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) in soft_reset_ready_check()
768 pm8001_dbg(pm8001_ha, INIT, "Firmware is ready for reset.\n"); in soft_reset_ready_check()
772 spin_lock_irqsave(&pm8001_ha->lock, flags); in soft_reset_ready_check()
773 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) { in soft_reset_ready_check()
774 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in soft_reset_ready_check()
775 pm8001_dbg(pm8001_ha, FAIL, in soft_reset_ready_check()
780 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, in soft_reset_ready_check()
782 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST); in soft_reset_ready_check()
785 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) & in soft_reset_ready_check()
788 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); in soft_reset_ready_check()
789 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); in soft_reset_ready_check()
790 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MSGU_SCRATCH_PAD1=0x%x, MSGU_SCRATCH_PAD2=0x%x\n", in soft_reset_ready_check()
792 pm8001_dbg(pm8001_ha, FAIL, in soft_reset_ready_check()
794 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)); in soft_reset_ready_check()
795 pm8001_dbg(pm8001_ha, FAIL, in soft_reset_ready_check()
797 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)); in soft_reset_ready_check()
798 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in soft_reset_ready_check()
801 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in soft_reset_ready_check()
812 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha) in pm8001_chip_soft_rst() argument
821 if (soft_reset_ready_check(pm8001_ha) != 0) { in pm8001_chip_soft_rst()
822 pm8001_dbg(pm8001_ha, FAIL, "FW is not ready\n"); in pm8001_chip_soft_rst()
829 spin_lock_irqsave(&pm8001_ha->lock, flags); in pm8001_chip_soft_rst()
830 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) { in pm8001_chip_soft_rst()
831 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in pm8001_chip_soft_rst()
832 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n", in pm8001_chip_soft_rst()
836 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP); in pm8001_chip_soft_rst()
837 pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", in pm8001_chip_soft_rst()
839 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0); in pm8001_chip_soft_rst()
841 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) { in pm8001_chip_soft_rst()
842 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in pm8001_chip_soft_rst()
843 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n", in pm8001_chip_soft_rst()
847 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1); in pm8001_chip_soft_rst()
848 pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", in pm8001_chip_soft_rst()
850 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0); in pm8001_chip_soft_rst()
852 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE); in pm8001_chip_soft_rst()
853 pm8001_dbg(pm8001_ha, INIT, "PCIE -Event Interrupt Enable = 0x%x\n", in pm8001_chip_soft_rst()
855 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0); in pm8001_chip_soft_rst()
857 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT); in pm8001_chip_soft_rst()
858 pm8001_dbg(pm8001_ha, INIT, "PCIE - Event Interrupt = 0x%x\n", in pm8001_chip_soft_rst()
860 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal); in pm8001_chip_soft_rst()
862 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE); in pm8001_chip_soft_rst()
863 pm8001_dbg(pm8001_ha, INIT, "PCIE -Error Interrupt Enable = 0x%x\n", in pm8001_chip_soft_rst()
865 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0); in pm8001_chip_soft_rst()
867 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT); in pm8001_chip_soft_rst()
868 pm8001_dbg(pm8001_ha, INIT, "PCIE - Error Interrupt = 0x%x\n", regVal); in pm8001_chip_soft_rst()
869 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal); in pm8001_chip_soft_rst()
872 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) in pm8001_chip_soft_rst()
878 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature); in pm8001_chip_soft_rst()
882 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { in pm8001_chip_soft_rst()
883 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in pm8001_chip_soft_rst()
884 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n", in pm8001_chip_soft_rst()
888 pm8001_dbg(pm8001_ha, INIT, in pm8001_chip_soft_rst()
890 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); in pm8001_chip_soft_rst()
893 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); in pm8001_chip_soft_rst()
904 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); in pm8001_chip_soft_rst()
905 pm8001_dbg(pm8001_ha, INIT, in pm8001_chip_soft_rst()
907 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); in pm8001_chip_soft_rst()
911 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); in pm8001_chip_soft_rst()
912 pm8001_dbg(pm8001_ha, INIT, in pm8001_chip_soft_rst()
915 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0); in pm8001_chip_soft_rst()
916 pm8001_dbg(pm8001_ha, INIT, in pm8001_chip_soft_rst()
918 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)); in pm8001_chip_soft_rst()
921 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); in pm8001_chip_soft_rst()
922 pm8001_dbg(pm8001_ha, INIT, in pm8001_chip_soft_rst()
925 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0); in pm8001_chip_soft_rst()
926 pm8001_dbg(pm8001_ha, INIT, in pm8001_chip_soft_rst()
928 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)); in pm8001_chip_soft_rst()
931 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); in pm8001_chip_soft_rst()
932 pm8001_dbg(pm8001_ha, INIT, "GSM 0x300048 - Write Data Parity Check Enable = 0x%x\n", in pm8001_chip_soft_rst()
934 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0); in pm8001_chip_soft_rst()
935 pm8001_dbg(pm8001_ha, INIT, in pm8001_chip_soft_rst()
937 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)); in pm8001_chip_soft_rst()
942 if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) { in pm8001_chip_soft_rst()
943 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in pm8001_chip_soft_rst()
944 pm8001_dbg(pm8001_ha, INIT, "Shift Bar4 to 0x%x failed\n", in pm8001_chip_soft_rst()
948 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET); in pm8001_chip_soft_rst()
949 pm8001_dbg(pm8001_ha, INIT, "GPIO Output Control Register: = 0x%x\n", in pm8001_chip_soft_rst()
953 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal); in pm8001_chip_soft_rst()
957 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { in pm8001_chip_soft_rst()
958 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in pm8001_chip_soft_rst()
959 pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n", in pm8001_chip_soft_rst()
963 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); in pm8001_chip_soft_rst()
964 pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting IOP/AAP1:= 0x%x\n", in pm8001_chip_soft_rst()
967 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); in pm8001_chip_soft_rst()
970 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); in pm8001_chip_soft_rst()
971 pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting BDMA/OSSP: = 0x%x\n", in pm8001_chip_soft_rst()
974 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); in pm8001_chip_soft_rst()
980 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); in pm8001_chip_soft_rst()
981 pm8001_dbg(pm8001_ha, INIT, in pm8001_chip_soft_rst()
985 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); in pm8001_chip_soft_rst()
992 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) { in pm8001_chip_soft_rst()
993 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in pm8001_chip_soft_rst()
994 pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n", in pm8001_chip_soft_rst()
998 pm8001_dbg(pm8001_ha, INIT, in pm8001_chip_soft_rst()
1000 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); in pm8001_chip_soft_rst()
1001 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); in pm8001_chip_soft_rst()
1011 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal); in pm8001_chip_soft_rst()
1012 …pm8001_dbg(pm8001_ha, INIT, "GSM (0x00004088 ==> 0x00007b88) - GSM Configuration and Reset is set … in pm8001_chip_soft_rst()
1013 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); in pm8001_chip_soft_rst()
1016 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); in pm8001_chip_soft_rst()
1018 pm8001_dbg(pm8001_ha, INIT, in pm8001_chip_soft_rst()
1021 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1); in pm8001_chip_soft_rst()
1022 pm8001_dbg(pm8001_ha, INIT, "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n", in pm8001_chip_soft_rst()
1023 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)); in pm8001_chip_soft_rst()
1025 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); in pm8001_chip_soft_rst()
1026 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2); in pm8001_chip_soft_rst()
1027 pm8001_dbg(pm8001_ha, INIT, in pm8001_chip_soft_rst()
1029 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)); in pm8001_chip_soft_rst()
1031 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); in pm8001_chip_soft_rst()
1032 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3); in pm8001_chip_soft_rst()
1033 pm8001_dbg(pm8001_ha, INIT, in pm8001_chip_soft_rst()
1035 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)); in pm8001_chip_soft_rst()
1039 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) { in pm8001_chip_soft_rst()
1040 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in pm8001_chip_soft_rst()
1041 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n", in pm8001_chip_soft_rst()
1045 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); in pm8001_chip_soft_rst()
1047 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal); in pm8001_chip_soft_rst()
1058 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & in pm8001_chip_soft_rst()
1063 regVal = pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1065 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT : ToggleVal 0x%x,MSGU_SCRATCH_PAD1 = 0x%x\n", in pm8001_chip_soft_rst()
1067 pm8001_dbg(pm8001_ha, FAIL, in pm8001_chip_soft_rst()
1069 pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1071 pm8001_dbg(pm8001_ha, FAIL, in pm8001_chip_soft_rst()
1073 pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1075 pm8001_dbg(pm8001_ha, FAIL, in pm8001_chip_soft_rst()
1077 pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1079 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in pm8001_chip_soft_rst()
1084 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); in pm8001_chip_soft_rst()
1085 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); in pm8001_chip_soft_rst()
1090 if (check_fw_ready(pm8001_ha) == -1) { in pm8001_chip_soft_rst()
1091 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); in pm8001_chip_soft_rst()
1093 pm8001_dbg(pm8001_ha, INIT, in pm8001_chip_soft_rst()
1096 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); in pm8001_chip_soft_rst()
1098 pm8001_dbg(pm8001_ha, INIT, in pm8001_chip_soft_rst()
1101 pm8001_dbg(pm8001_ha, INIT, in pm8001_chip_soft_rst()
1103 pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1105 pm8001_dbg(pm8001_ha, INIT, in pm8001_chip_soft_rst()
1107 pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1109 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in pm8001_chip_soft_rst()
1113 pm8001_bar4_shift(pm8001_ha, 0); in pm8001_chip_soft_rst()
1114 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in pm8001_chip_soft_rst()
1116 pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n"); in pm8001_chip_soft_rst()
1120 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha) in pm8001_hw_chip_rst() argument
1124 pm8001_dbg(pm8001_ha, INIT, "chip reset start\n"); in pm8001_hw_chip_rst()
1127 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); in pm8001_hw_chip_rst()
1129 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); in pm8001_hw_chip_rst()
1135 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); in pm8001_hw_chip_rst()
1137 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal); in pm8001_hw_chip_rst()
1148 pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n"); in pm8001_hw_chip_rst()
1155 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha) in pm8001_chip_iounmap() argument
1169 if (pm8001_ha->io_mem[logical].memvirtaddr) { in pm8001_chip_iounmap()
1170 iounmap(pm8001_ha->io_mem[logical].memvirtaddr); in pm8001_chip_iounmap()
1182 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha) in pm8001_chip_intx_interrupt_enable() argument
1184 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); in pm8001_chip_intx_interrupt_enable()
1185 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); in pm8001_chip_intx_interrupt_enable()
1193 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha) in pm8001_chip_intx_interrupt_disable() argument
1195 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL); in pm8001_chip_intx_interrupt_disable()
1206 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha, in pm8001_chip_msix_interrupt_enable() argument
1213 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE); in pm8001_chip_msix_interrupt_enable()
1215 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value); in pm8001_chip_msix_interrupt_enable()
1225 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha, in pm8001_chip_msix_interrupt_disable() argument
1231 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE); in pm8001_chip_msix_interrupt_disable()
1241 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) in pm8001_chip_interrupt_enable() argument
1244 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0); in pm8001_chip_interrupt_enable()
1246 pm8001_chip_intx_interrupt_enable(pm8001_ha); in pm8001_chip_interrupt_enable()
1256 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) in pm8001_chip_interrupt_disable() argument
1259 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0); in pm8001_chip_interrupt_disable()
1261 pm8001_chip_intx_interrupt_disable(pm8001_ha); in pm8001_chip_interrupt_disable()
1315 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha, in pm8001_mpi_build_cmd() argument
1323 int q_index = circularQ - pm8001_ha->inbnd_q_tbl; in pm8001_mpi_build_cmd()
1326 if (WARN_ON(q_index >= pm8001_ha->max_q_num)) in pm8001_mpi_build_cmd()
1330 rv = pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size, in pm8001_mpi_build_cmd()
1333 pm8001_dbg(pm8001_ha, IO, "No free mpi buffer\n"); in pm8001_mpi_build_cmd()
1338 if (nb > (pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr))) in pm8001_mpi_build_cmd()
1339 nb = pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr); in pm8001_mpi_build_cmd()
1341 if (nb + sizeof(struct mpi_msg_hdr) < pm8001_ha->iomb_size) in pm8001_mpi_build_cmd()
1342 memset(pMessage + nb, 0, pm8001_ha->iomb_size - in pm8001_mpi_build_cmd()
1352 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar, in pm8001_mpi_build_cmd()
1354 pm8001_dbg(pm8001_ha, DEVIO, in pm8001_mpi_build_cmd()
1363 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg, in pm8001_mpi_msg_free_set() argument
1372 circularQ->consumer_idx * pm8001_ha->iomb_size); in pm8001_mpi_msg_free_set()
1374 pm8001_dbg(pm8001_ha, FAIL, in pm8001_mpi_msg_free_set()
1381 pm8001_dbg(pm8001_ha, FAIL, in pm8001_mpi_msg_free_set()
1391 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset, in pm8001_mpi_msg_free_set()
1396 pm8001_dbg(pm8001_ha, IO, " CI=%d PI=%d\n", in pm8001_mpi_msg_free_set()
1409 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha, in pm8001_mpi_msg_consume() argument
1423 circularQ->consumer_idx * pm8001_ha->iomb_size); in pm8001_mpi_msg_consume()
1427 pm8001_dbg(pm8001_ha, DEVIO, in pm8001_mpi_msg_consume()
1439 pm8001_dbg(pm8001_ha, IO, in pm8001_mpi_msg_consume()
1454 pm8001_cw32(pm8001_ha, in pm8001_mpi_msg_consume()
1467 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, in pm8001_mpi_msg_consume()
1518 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha; in pm8001_work_fn() local
1525 spin_lock_irqsave(&pm8001_ha->lock, flags); in pm8001_work_fn()
1530 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in pm8001_work_fn()
1537 ccb = &pm8001_ha->ccb_info[i]; in pm8001_work_fn()
1543 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in pm8001_work_fn()
1559 …pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upp… in pm8001_work_fn()
1561 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); in pm8001_work_fn()
1562 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in pm8001_work_fn()
1565 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); in pm8001_work_fn()
1567 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in pm8001_work_fn()
1576 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha; in pm8001_work_fn() local
1580 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); in pm8001_work_fn()
1585 pm8001_dbg(pm8001_ha, IO, "...Task on lu\n"); in pm8001_work_fn()
1587 pm8001_dbg(pm8001_ha, IO, "...Task NOT on lu\n"); in pm8001_work_fn()
1589 pm8001_dbg(pm8001_ha, DEVIO, "...query task failed!!!\n"); in pm8001_work_fn()
1591 spin_lock_irqsave(&pm8001_ha->lock, flags); in pm8001_work_fn()
1597 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in pm8001_work_fn()
1607 ccb = &pm8001_ha->ccb_info[i]; in pm8001_work_fn()
1613 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in pm8001_work_fn()
1625 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in pm8001_work_fn()
1634 pm8001_dbg(pm8001_ha, IO, "...Reset phy\n"); in pm8001_work_fn()
1641 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in pm8001_work_fn()
1646 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in pm8001_work_fn()
1648 pm8001_dbg(pm8001_ha, IO, "...Reset phy\n"); in pm8001_work_fn()
1654 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev); in pm8001_work_fn()
1655 pm8001_dbg(pm8001_ha, IO, "...Complete\n"); in pm8001_work_fn()
1677 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data, in pm8001_handle_event() argument
1685 pw->pm8001_ha = pm8001_ha; in pm8001_handle_event()
1696 static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha, in pm8001_send_abort_all() argument
1709 pm8001_dbg(pm8001_ha, FAIL, "dev is null\n"); in pm8001_send_abort_all()
1715 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n"); in pm8001_send_abort_all()
1721 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); in pm8001_send_abort_all()
1727 ccb = &pm8001_ha->ccb_info[ccb_tag]; in pm8001_send_abort_all()
1733 circularQ = &pm8001_ha->inbnd_q_tbl[0]; in pm8001_send_abort_all()
1740 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, in pm8001_send_abort_all()
1744 pm8001_tag_free(pm8001_ha, ccb_tag); in pm8001_send_abort_all()
1749 static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha, in pm8001_send_read_log() argument
1765 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n"); in pm8001_send_read_log()
1770 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag); in pm8001_send_read_log()
1773 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate tag !!!\n"); in pm8001_send_read_log()
1783 pm8001_tag_free(pm8001_ha, ccb_tag); in pm8001_send_read_log()
1784 pm8001_dbg(pm8001_ha, FAIL, in pm8001_send_read_log()
1791 ccb = &pm8001_ha->ccb_info[ccb_tag]; in pm8001_send_read_log()
1800 circularQ = &pm8001_ha->inbnd_q_tbl[0]; in pm8001_send_read_log()
1815 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, in pm8001_send_read_log()
1819 pm8001_tag_free(pm8001_ha, ccb_tag); in pm8001_send_read_log()
1836 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb) in mpi_ssp_completion() argument
1851 ccb = &pm8001_ha->ccb_info[tag]; in mpi_ssp_completion()
1863 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status); in mpi_ssp_completion()
1870 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n", in mpi_ssp_completion()
1874 pm8001_dbg(pm8001_ha, IOERR, in mpi_ssp_completion()
1880 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS,param = %d\n", in mpi_ssp_completion()
1890 sas_ssp_task_response(pm8001_ha->dev, t, iu); in mpi_ssp_completion()
1896 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); in mpi_ssp_completion()
1902 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW,param = %d\n", in mpi_ssp_completion()
1911 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); in mpi_ssp_completion()
1916 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); in mpi_ssp_completion()
1923 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); in mpi_ssp_completion()
1929 pm8001_dbg(pm8001_ha, IO, in mpi_ssp_completion()
1936 pm8001_dbg(pm8001_ha, IO, in mpi_ssp_completion()
1943 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); in mpi_ssp_completion()
1949 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); in mpi_ssp_completion()
1954 pm8001_handle_event(pm8001_ha, in mpi_ssp_completion()
1959 pm8001_dbg(pm8001_ha, IO, in mpi_ssp_completion()
1966 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); in mpi_ssp_completion()
1972 pm8001_dbg(pm8001_ha, IO, in mpi_ssp_completion()
1979 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); in mpi_ssp_completion()
1985 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); in mpi_ssp_completion()
1990 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); in mpi_ssp_completion()
1995 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); in mpi_ssp_completion()
2001 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); in mpi_ssp_completion()
2006 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); in mpi_ssp_completion()
2011 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); in mpi_ssp_completion()
2015 pm8001_handle_event(pm8001_ha, in mpi_ssp_completion()
2020 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); in mpi_ssp_completion()
2025 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n"); in mpi_ssp_completion()
2030 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"); in mpi_ssp_completion()
2035 pm8001_dbg(pm8001_ha, IO, in mpi_ssp_completion()
2042 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); in mpi_ssp_completion()
2048 pm8001_dbg(pm8001_ha, IO, "scsi_status = %x\n", in mpi_ssp_completion()
2056 …pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by… in mpi_ssp_completion()
2058 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); in mpi_ssp_completion()
2061 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); in mpi_ssp_completion()
2068 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb) in mpi_ssp_event() argument
2082 ccb = &pm8001_ha->ccb_info[tag]; in mpi_ssp_event()
2086 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event); in mpi_ssp_event()
2090 pm8001_dbg(pm8001_ha, DEVIO, "port_id = %x,device_id = %x\n", in mpi_ssp_event()
2094 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); in mpi_ssp_event()
2102 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); in mpi_ssp_event()
2103 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK); in mpi_ssp_event()
2106 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); in mpi_ssp_event()
2112 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); in mpi_ssp_event()
2118 pm8001_dbg(pm8001_ha, IO, in mpi_ssp_event()
2125 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); in mpi_ssp_event()
2131 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); in mpi_ssp_event()
2136 pm8001_handle_event(pm8001_ha, in mpi_ssp_event()
2141 pm8001_dbg(pm8001_ha, IO, in mpi_ssp_event()
2148 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); in mpi_ssp_event()
2154 pm8001_dbg(pm8001_ha, IO, in mpi_ssp_event()
2161 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); in mpi_ssp_event()
2167 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); in mpi_ssp_event()
2172 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); in mpi_ssp_event()
2173 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT); in mpi_ssp_event()
2176 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); in mpi_ssp_event()
2181 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); in mpi_ssp_event()
2186 pm8001_dbg(pm8001_ha, IO, in mpi_ssp_event()
2192 pm8001_dbg(pm8001_ha, IO, in mpi_ssp_event()
2198 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); in mpi_ssp_event()
2203 pm8001_dbg(pm8001_ha, IO, in mpi_ssp_event()
2209 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); in mpi_ssp_event()
2212 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event); in mpi_ssp_event()
2224 …pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upp… in mpi_ssp_event()
2226 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); in mpi_ssp_event()
2229 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); in mpi_ssp_event()
2237 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) in mpi_sata_completion() argument
2261 pm8001_dbg(pm8001_ha, FAIL, "tag null\n"); in mpi_sata_completion()
2264 ccb = &pm8001_ha->ccb_info[tag]; in mpi_sata_completion()
2270 pm8001_dbg(pm8001_ha, FAIL, "ccb null\n"); in mpi_sata_completion()
2278 pm8001_dbg(pm8001_ha, FAIL, "task null\n"); in mpi_sata_completion()
2284 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n"); in mpi_sata_completion()
2290 pm8001_dbg(pm8001_ha, FAIL, "ts null\n"); in mpi_sata_completion()
2295 pm8001_dbg(pm8001_ha, IOERR, in mpi_sata_completion()
2305 sata_addr_low[i] = pm8001_ha->sas_addr[j]; in mpi_sata_completion()
2307 sata_addr_hi[i] = pm8001_ha->sas_addr[j]; in mpi_sata_completion()
2329 pm8001_dbg(pm8001_ha, FAIL, in mpi_sata_completion()
2334 pm8001_dbg(pm8001_ha, FAIL, in mpi_sata_completion()
2341 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); in mpi_sata_completion()
2352 pm8001_send_abort_all(pm8001_ha, pm8001_dev); in mpi_sata_completion()
2354 pm8001_tag_free(pm8001_ha, tag); in mpi_sata_completion()
2363 pm8001_dbg(pm8001_ha, IO, in mpi_sata_completion()
2371 pm8001_dbg(pm8001_ha, IO, in mpi_sata_completion()
2376 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n", in mpi_sata_completion()
2380 pm8001_dbg(pm8001_ha, IO, "other len = %d\n", in mpi_sata_completion()
2388 pm8001_dbg(pm8001_ha, IO, in mpi_sata_completion()
2395 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n"); in mpi_sata_completion()
2404 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param); in mpi_sata_completion()
2412 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); in mpi_sata_completion()
2419 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); in mpi_sata_completion()
2426 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); in mpi_sata_completion()
2434 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); in mpi_sata_completion()
2442 pm8001_dbg(pm8001_ha, IO, in mpi_sata_completion()
2451 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); in mpi_sata_completion()
2459 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); in mpi_sata_completion()
2463 pm8001_handle_event(pm8001_ha, in mpi_sata_completion()
2468 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); in mpi_sata_completion()
2473 pm8001_dbg(pm8001_ha, IO, in mpi_sata_completion()
2479 pm8001_handle_event(pm8001_ha, in mpi_sata_completion()
2484 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); in mpi_sata_completion()
2489 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); in mpi_sata_completion()
2497 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"); in mpi_sata_completion()
2501 pm8001_handle_event(pm8001_ha, in mpi_sata_completion()
2506 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); in mpi_sata_completion()
2511 pm8001_dbg(pm8001_ha, IO, in mpi_sata_completion()
2520 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); in mpi_sata_completion()
2527 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"); in mpi_sata_completion()
2534 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n"); in mpi_sata_completion()
2541 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"); in mpi_sata_completion()
2548 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); in mpi_sata_completion()
2555 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); in mpi_sata_completion()
2562 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); in mpi_sata_completion()
2569 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); in mpi_sata_completion()
2573 pm8001_handle_event(pm8001_ha, pm8001_dev, in mpi_sata_completion()
2577 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); in mpi_sata_completion()
2582 pm8001_dbg(pm8001_ha, IO, " IO_DS_IN_RECOVERY\n"); in mpi_sata_completion()
2589 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n"); in mpi_sata_completion()
2593 pm8001_handle_event(pm8001_ha, pm8001_dev, in mpi_sata_completion()
2597 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); in mpi_sata_completion()
2602 pm8001_dbg(pm8001_ha, IO, in mpi_sata_completion()
2611 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); in mpi_sata_completion()
2625 pm8001_dbg(pm8001_ha, FAIL, in mpi_sata_completion()
2628 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); in mpi_sata_completion()
2631 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); in mpi_sata_completion()
2636 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb) in mpi_sata_event() argument
2650 ccb = &pm8001_ha->ccb_info[tag]; in mpi_sata_event()
2656 pm8001_dbg(pm8001_ha, FAIL, "No CCB !!!. returning\n"); in mpi_sata_event()
2659 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event); in mpi_sata_event()
2664 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id); in mpi_sata_event()
2667 pm8001_send_read_log(pm8001_ha, pm8001_dev); in mpi_sata_event()
2671 ccb = &pm8001_ha->ccb_info[tag]; in mpi_sata_event()
2675 pm8001_dbg(pm8001_ha, FAIL, "sata IO status 0x%x\n", event); in mpi_sata_event()
2679 pm8001_dbg(pm8001_ha, DEVIO, in mpi_sata_event()
2684 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); in mpi_sata_event()
2692 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); in mpi_sata_event()
2697 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); in mpi_sata_event()
2703 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"); in mpi_sata_event()
2709 pm8001_dbg(pm8001_ha, IO, in mpi_sata_event()
2716 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); in mpi_sata_event()
2722 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); in mpi_sata_event()
2726 pm8001_handle_event(pm8001_ha, in mpi_sata_event()
2731 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); in mpi_sata_event()
2736 pm8001_dbg(pm8001_ha, IO, in mpi_sata_event()
2743 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); in mpi_sata_event()
2749 pm8001_dbg(pm8001_ha, IO, in mpi_sata_event()
2756 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n"); in mpi_sata_event()
2761 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n"); in mpi_sata_event()
2766 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n"); in mpi_sata_event()
2771 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); in mpi_sata_event()
2776 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n"); in mpi_sata_event()
2781 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n"); in mpi_sata_event()
2786 pm8001_dbg(pm8001_ha, IO, in mpi_sata_event()
2792 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n"); in mpi_sata_event()
2797 pm8001_dbg(pm8001_ha, IO, in mpi_sata_event()
2803 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n"); in mpi_sata_event()
2806 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n"); in mpi_sata_event()
2811 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event); in mpi_sata_event()
2823 pm8001_dbg(pm8001_ha, FAIL, in mpi_sata_event()
2826 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); in mpi_sata_event()
2829 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag); in mpi_sata_event()
2835 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb) in mpi_smp_completion() argument
2850 ccb = &pm8001_ha->ccb_info[tag]; in mpi_smp_completion()
2855 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status); in mpi_smp_completion()
2856 pm8001_dbg(pm8001_ha, IOERR, in mpi_smp_completion()
2865 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n"); in mpi_smp_completion()
2872 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n"); in mpi_smp_completion()
2879 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n"); in mpi_smp_completion()
2887 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n"); in mpi_smp_completion()
2892 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n"); in mpi_smp_completion()
2897 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n"); in mpi_smp_completion()
2902 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n"); in mpi_smp_completion()
2907 pm8001_dbg(pm8001_ha, IO, in mpi_smp_completion()
2914 pm8001_dbg(pm8001_ha, IO, in mpi_smp_completion()
2921 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n"); in mpi_smp_completion()
2927 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"); in mpi_smp_completion()
2931 pm8001_handle_event(pm8001_ha, in mpi_smp_completion()
2936 pm8001_dbg(pm8001_ha, IO, in mpi_smp_completion()
2943 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"); in mpi_smp_completion()
2949 pm8001_dbg(pm8001_ha, IO, in mpi_smp_completion()
2956 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n"); in mpi_smp_completion()
2961 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n"); in mpi_smp_completion()
2967 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n"); in mpi_smp_completion()
2972 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n"); in mpi_smp_completion()
2978 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n"); in mpi_smp_completion()
2983 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n"); in mpi_smp_completion()
2989 pm8001_dbg(pm8001_ha, IO, in mpi_smp_completion()
2996 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); in mpi_smp_completion()
3008 …pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by… in mpi_smp_completion()
3010 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); in mpi_smp_completion()
3013 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); in mpi_smp_completion()
3019 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, in pm8001_mpi_set_dev_state_resp() argument
3025 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; in pm8001_mpi_set_dev_state_resp()
3031 pm8001_dbg(pm8001_ha, MSG, "Set device id = 0x%x state from 0x%x to 0x%x status = 0x%x!\n", in pm8001_mpi_set_dev_state_resp()
3036 pm8001_tag_free(pm8001_ha, tag); in pm8001_mpi_set_dev_state_resp()
3039 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) in pm8001_mpi_set_nvmd_resp() argument
3044 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; in pm8001_mpi_set_nvmd_resp()
3046 complete(pm8001_ha->nvmd_completion); in pm8001_mpi_set_nvmd_resp()
3047 pm8001_dbg(pm8001_ha, MSG, "Set nvm data complete!\n"); in pm8001_mpi_set_nvmd_resp()
3049 pm8001_dbg(pm8001_ha, FAIL, "Set nvm data error!\n"); in pm8001_mpi_set_nvmd_resp()
3054 pm8001_tag_free(pm8001_ha, tag); in pm8001_mpi_set_nvmd_resp()
3058 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) in pm8001_mpi_get_nvmd_resp() argument
3064 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; in pm8001_mpi_get_nvmd_resp()
3068 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr; in pm8001_mpi_get_nvmd_resp()
3071 pm8001_dbg(pm8001_ha, MSG, "Get nvm data complete!\n"); in pm8001_mpi_get_nvmd_resp()
3073 pm8001_dbg(pm8001_ha, FAIL, "Get nvm data error!\n"); in pm8001_mpi_get_nvmd_resp()
3074 complete(pm8001_ha->nvmd_completion); in pm8001_mpi_get_nvmd_resp()
3080 pm8001_dbg(pm8001_ha, MSG, "Get NVMD success, IR=1\n"); in pm8001_mpi_get_nvmd_resp()
3083 memcpy(pm8001_ha->sas_addr, in pm8001_mpi_get_nvmd_resp()
3086 pm8001_dbg(pm8001_ha, MSG, "Get SAS address from VPD successfully!\n"); in pm8001_mpi_get_nvmd_resp()
3097 pm8001_dbg(pm8001_ha, MSG, in pm8001_mpi_get_nvmd_resp()
3102 pm8001_dbg(pm8001_ha, MSG, in pm8001_mpi_get_nvmd_resp()
3110 pm8001_ha->memoryMap.region[NVMD].virt_ptr, in pm8001_mpi_get_nvmd_resp()
3117 complete(pm8001_ha->nvmd_completion); in pm8001_mpi_get_nvmd_resp()
3118 pm8001_dbg(pm8001_ha, MSG, "Get nvmd data complete!\n"); in pm8001_mpi_get_nvmd_resp()
3121 pm8001_tag_free(pm8001_ha, tag); in pm8001_mpi_get_nvmd_resp()
3124 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb) in pm8001_mpi_local_phy_ctl() argument
3134 pm8001_dbg(pm8001_ha, MSG, in pm8001_mpi_local_phy_ctl()
3138 pm8001_dbg(pm8001_ha, MSG, in pm8001_mpi_local_phy_ctl()
3141 pm8001_ha->phy[phy_id].reset_success = true; in pm8001_mpi_local_phy_ctl()
3143 if (pm8001_ha->phy[phy_id].enable_completion) { in pm8001_mpi_local_phy_ctl()
3144 complete(pm8001_ha->phy[phy_id].enable_completion); in pm8001_mpi_local_phy_ctl()
3145 pm8001_ha->phy[phy_id].enable_completion = NULL; in pm8001_mpi_local_phy_ctl()
3147 pm8001_tag_free(pm8001_ha, tag); in pm8001_mpi_local_phy_ctl()
3162 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i) in pm8001_bytes_dmaed() argument
3164 struct pm8001_phy *phy = &pm8001_ha->phy[i]; in pm8001_bytes_dmaed()
3187 pm8001_dbg(pm8001_ha, MSG, "phy %d byte dmaded.\n", i); in pm8001_bytes_dmaed()
3240 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha; in pm8001_get_attached_sas_addr() local
3242 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr); in pm8001_get_attached_sas_addr()
3262 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha, in pm8001_hw_event_ack_req() argument
3271 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum]; in pm8001_hw_event_ack_req()
3277 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, in pm8001_hw_event_ack_req()
3281 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3290 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) in hw_event_sas_phy_up() argument
3303 struct pm8001_port *port = &pm8001_ha->port[port_id]; in hw_event_sas_phy_up()
3304 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; in hw_event_sas_phy_up()
3309 pm8001_dbg(pm8001_ha, MSG, in hw_event_sas_phy_up()
3315 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n"); in hw_event_sas_phy_up()
3318 pm8001_dbg(pm8001_ha, MSG, "end device.\n"); in hw_event_sas_phy_up()
3319 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id, in hw_event_sas_phy_up()
3325 pm8001_dbg(pm8001_ha, MSG, "expander device.\n"); in hw_event_sas_phy_up()
3330 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n"); in hw_event_sas_phy_up()
3335 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n", in hw_event_sas_phy_up()
3354 if (pm8001_ha->flags == PM8001F_RUN_TIME) in hw_event_sas_phy_up()
3356 pm8001_bytes_dmaed(pm8001_ha, phy_id); in hw_event_sas_phy_up()
3365 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb) in hw_event_sata_phy_up() argument
3378 struct pm8001_port *port = &pm8001_ha->port[port_id]; in hw_event_sata_phy_up()
3379 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; in hw_event_sata_phy_up()
3381 pm8001_dbg(pm8001_ha, DEVIO, "HW_EVENT_SATA_PHY_UP port id = %d, phy id = %d\n", in hw_event_sata_phy_up()
3399 pm8001_bytes_dmaed(pm8001_ha, phy_id); in hw_event_sata_phy_up()
3408 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb) in hw_event_phy_down() argument
3419 struct pm8001_port *port = &pm8001_ha->port[port_id]; in hw_event_phy_down()
3420 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; in hw_event_phy_down()
3430 pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n", in hw_event_phy_down()
3432 pm8001_dbg(pm8001_ha, MSG, in hw_event_phy_down()
3435 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, in hw_event_phy_down()
3439 pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n", in hw_event_phy_down()
3443 pm8001_dbg(pm8001_ha, MSG, in hw_event_phy_down()
3448 pm8001_dbg(pm8001_ha, MSG, " phy Down and PORT_LOSTCOMM\n"); in hw_event_phy_down()
3449 pm8001_dbg(pm8001_ha, MSG, in hw_event_phy_down()
3452 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, in hw_event_phy_down()
3457 pm8001_dbg(pm8001_ha, DEVIO, " phy Down and(default) = %x\n", in hw_event_phy_down()
3474 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) in pm8001_mpi_reg_resp() argument
3485 ccb = &pm8001_ha->ccb_info[htag]; in pm8001_mpi_reg_resp()
3489 pm8001_dbg(pm8001_ha, MSG, " register device is status = %d\n", in pm8001_mpi_reg_resp()
3493 pm8001_dbg(pm8001_ha, MSG, "DEVREG_SUCCESS\n"); in pm8001_mpi_reg_resp()
3497 pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_OUT_OF_RESOURCE\n"); in pm8001_mpi_reg_resp()
3500 pm8001_dbg(pm8001_ha, MSG, in pm8001_mpi_reg_resp()
3504 pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_INVALID_PHY_ID\n"); in pm8001_mpi_reg_resp()
3507 pm8001_dbg(pm8001_ha, MSG, in pm8001_mpi_reg_resp()
3511 pm8001_dbg(pm8001_ha, MSG, in pm8001_mpi_reg_resp()
3515 pm8001_dbg(pm8001_ha, MSG, in pm8001_mpi_reg_resp()
3519 pm8001_dbg(pm8001_ha, MSG, in pm8001_mpi_reg_resp()
3523 pm8001_dbg(pm8001_ha, MSG, in pm8001_mpi_reg_resp()
3530 pm8001_tag_free(pm8001_ha, htag); in pm8001_mpi_reg_resp()
3534 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) in pm8001_mpi_dereg_resp() argument
3544 pm8001_dbg(pm8001_ha, MSG, in pm8001_mpi_dereg_resp()
3555 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, in pm8001_mpi_fw_flash_update_resp() argument
3562 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag]; in pm8001_mpi_fw_flash_update_resp()
3566 pm8001_dbg(pm8001_ha, MSG, in pm8001_mpi_fw_flash_update_resp()
3570 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_IN_PROGRESS\n"); in pm8001_mpi_fw_flash_update_resp()
3573 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HDR_ERR\n"); in pm8001_mpi_fw_flash_update_resp()
3576 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_OFFSET_ERR\n"); in pm8001_mpi_fw_flash_update_resp()
3579 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_CRC_ERR\n"); in pm8001_mpi_fw_flash_update_resp()
3582 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_LENGTH_ERR\n"); in pm8001_mpi_fw_flash_update_resp()
3585 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HW_ERR\n"); in pm8001_mpi_fw_flash_update_resp()
3588 pm8001_dbg(pm8001_ha, MSG, in pm8001_mpi_fw_flash_update_resp()
3592 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_DISABLED\n"); in pm8001_mpi_fw_flash_update_resp()
3595 pm8001_dbg(pm8001_ha, DEVIO, "No matched status = %d\n", in pm8001_mpi_fw_flash_update_resp()
3602 pm8001_tag_free(pm8001_ha, tag); in pm8001_mpi_fw_flash_update_resp()
3603 complete(pm8001_ha->nvmd_completion); in pm8001_mpi_fw_flash_update_resp()
3607 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb) in pm8001_mpi_general_event() argument
3614 pm8001_dbg(pm8001_ha, MSG, " status = 0x%x\n", status); in pm8001_mpi_general_event()
3616 pm8001_dbg(pm8001_ha, MSG, "inb_IOMB_payload[0x%x] 0x%x,\n", in pm8001_mpi_general_event()
3622 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb) in pm8001_mpi_task_abort_resp() argument
3638 pm8001_dbg(pm8001_ha, FAIL, " TAG NULL. RETURNING !!!\n"); in pm8001_mpi_task_abort_resp()
3643 ccb = &pm8001_ha->ccb_info[tag]; in pm8001_mpi_task_abort_resp()
3648 pm8001_dbg(pm8001_ha, FAIL, " TASK NULL. RETURNING !!!\n"); in pm8001_mpi_task_abort_resp()
3653 pm8001_dbg(pm8001_ha, FAIL, "task abort failed status 0x%x ,tag = 0x%x, scp= 0x%x\n", in pm8001_mpi_task_abort_resp()
3657 pm8001_dbg(pm8001_ha, EH, "IO_SUCCESS\n"); in pm8001_mpi_task_abort_resp()
3662 pm8001_dbg(pm8001_ha, EH, "IO_NOT_VALID\n"); in pm8001_mpi_task_abort_resp()
3671 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag); in pm8001_mpi_task_abort_resp()
3689 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb) in mpi_hw_event() argument
3703 struct sas_ha_struct *sas_ha = pm8001_ha->sas; in mpi_hw_event()
3704 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; in mpi_hw_event()
3706 pm8001_dbg(pm8001_ha, DEVIO, in mpi_hw_event()
3711 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS status = %x\n", in mpi_hw_event()
3716 if (pm8001_ha->flags == PM8001F_RUN_TIME && in mpi_hw_event()
3723 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n"); in mpi_hw_event()
3724 hw_event_sas_phy_up(pm8001_ha, piomb); in mpi_hw_event()
3727 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n"); in mpi_hw_event()
3728 hw_event_sata_phy_up(pm8001_ha, piomb); in mpi_hw_event()
3731 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_STOP_STATUS status = %x\n", in mpi_hw_event()
3737 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n"); in mpi_hw_event()
3741 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n"); in mpi_hw_event()
3745 hw_event_phy_down(pm8001_ha, piomb); in mpi_hw_event()
3748 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n"); in mpi_hw_event()
3756 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n"); in mpi_hw_event()
3757 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, in mpi_hw_event()
3765 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n"); in mpi_hw_event()
3771 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n"); in mpi_hw_event()
3778 pm8001_dbg(pm8001_ha, MSG, in mpi_hw_event()
3780 pm8001_hw_event_ack_req(pm8001_ha, 0, in mpi_hw_event()
3787 pm8001_dbg(pm8001_ha, MSG, in mpi_hw_event()
3789 pm8001_hw_event_ack_req(pm8001_ha, 0, in mpi_hw_event()
3797 pm8001_dbg(pm8001_ha, MSG, in mpi_hw_event()
3799 pm8001_hw_event_ack_req(pm8001_ha, 0, in mpi_hw_event()
3807 pm8001_dbg(pm8001_ha, MSG, in mpi_hw_event()
3809 pm8001_hw_event_ack_req(pm8001_ha, 0, in mpi_hw_event()
3817 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n"); in mpi_hw_event()
3820 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n"); in mpi_hw_event()
3827 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n"); in mpi_hw_event()
3828 pm8001_hw_event_ack_req(pm8001_ha, 0, in mpi_hw_event()
3833 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n"); in mpi_hw_event()
3837 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n"); in mpi_hw_event()
3843 pm8001_dbg(pm8001_ha, MSG, in mpi_hw_event()
3845 pm8001_hw_event_ack_req(pm8001_ha, 0, in mpi_hw_event()
3853 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n"); in mpi_hw_event()
3859 pm8001_dbg(pm8001_ha, MSG, in mpi_hw_event()
3866 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n"); in mpi_hw_event()
3869 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n"); in mpi_hw_event()
3872 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n"); in mpi_hw_event()
3875 pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type = %x\n", in mpi_hw_event()
3887 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb) in process_one_iomb() argument
3892 pm8001_dbg(pm8001_ha, MSG, "process_one_iomb:\n"); in process_one_iomb()
3896 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n"); in process_one_iomb()
3899 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n"); in process_one_iomb()
3900 mpi_hw_event(pm8001_ha, piomb); in process_one_iomb()
3903 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n"); in process_one_iomb()
3904 mpi_ssp_completion(pm8001_ha, piomb); in process_one_iomb()
3907 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n"); in process_one_iomb()
3908 mpi_smp_completion(pm8001_ha, piomb); in process_one_iomb()
3911 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n"); in process_one_iomb()
3912 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb); in process_one_iomb()
3915 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n"); in process_one_iomb()
3916 pm8001_mpi_reg_resp(pm8001_ha, piomb); in process_one_iomb()
3919 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n"); in process_one_iomb()
3920 pm8001_mpi_dereg_resp(pm8001_ha, piomb); in process_one_iomb()
3923 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n"); in process_one_iomb()
3926 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n"); in process_one_iomb()
3927 mpi_sata_completion(pm8001_ha, piomb); in process_one_iomb()
3930 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n"); in process_one_iomb()
3931 mpi_sata_event(pm8001_ha, piomb); in process_one_iomb()
3934 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n"); in process_one_iomb()
3935 mpi_ssp_event(pm8001_ha, piomb); in process_one_iomb()
3938 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n"); in process_one_iomb()
3942 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n"); in process_one_iomb()
3946 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_INFO\n"); in process_one_iomb()
3949 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n"); in process_one_iomb()
3950 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb); in process_one_iomb()
3953 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n"); in process_one_iomb()
3956 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n"); in process_one_iomb()
3959 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n"); in process_one_iomb()
3960 pm8001_mpi_general_event(pm8001_ha, piomb); in process_one_iomb()
3963 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n"); in process_one_iomb()
3964 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); in process_one_iomb()
3967 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n"); in process_one_iomb()
3968 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); in process_one_iomb()
3971 pm8001_dbg(pm8001_ha, MSG, in process_one_iomb()
3975 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n"); in process_one_iomb()
3978 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n"); in process_one_iomb()
3981 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n"); in process_one_iomb()
3984 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n"); in process_one_iomb()
3987 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n"); in process_one_iomb()
3988 pm8001_mpi_task_abort_resp(pm8001_ha, piomb); in process_one_iomb()
3991 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n"); in process_one_iomb()
3992 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb); in process_one_iomb()
3995 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n"); in process_one_iomb()
3996 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb); in process_one_iomb()
3999 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n"); in process_one_iomb()
4002 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n"); in process_one_iomb()
4003 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb); in process_one_iomb()
4006 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n"); in process_one_iomb()
4009 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n"); in process_one_iomb()
4012 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_RE_INITIALIZE\n"); in process_one_iomb()
4015 pm8001_dbg(pm8001_ha, DEVIO, in process_one_iomb()
4022 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) in process_oq() argument
4030 spin_lock_irqsave(&pm8001_ha->lock, flags); in process_oq()
4031 circularQ = &pm8001_ha->outbnd_q_tbl[vec]; in process_oq()
4033 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc); in process_oq()
4036 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4)); in process_oq()
4038 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1, in process_oq()
4051 spin_unlock_irqrestore(&pm8001_ha->lock, flags); in process_oq()
4089 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha, in pm8001_chip_smp_req() argument
4107 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE); in pm8001_chip_smp_req()
4113 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE); in pm8001_chip_smp_req()
4126 circularQ = &pm8001_ha->inbnd_q_tbl[0]; in pm8001_chip_smp_req()
4137 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, in pm8001_chip_smp_req()
4145 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, in pm8001_chip_smp_req()
4148 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, in pm8001_chip_smp_req()
4158 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha, in pm8001_chip_ssp_io_req() argument
4184 circularQ = &pm8001_ha->inbnd_q_tbl[0]; in pm8001_chip_ssp_io_req()
4205 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd, in pm8001_chip_ssp_io_req()
4210 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha, in pm8001_chip_sata_req() argument
4227 circularQ = &pm8001_ha->inbnd_q_tbl[0]; in pm8001_chip_sata_req()
4231 pm8001_dbg(pm8001_ha, IO, "no data\n"); in pm8001_chip_sata_req()
4236 pm8001_dbg(pm8001_ha, IO, "FPDMA\n"); in pm8001_chip_sata_req()
4239 pm8001_dbg(pm8001_ha, IO, "DMA\n"); in pm8001_chip_sata_req()
4242 pm8001_dbg(pm8001_ha, IO, "PIO\n"); in pm8001_chip_sata_req()
4299 pm8001_dbg(pm8001_ha, FAIL, in pm8001_chip_sata_req()
4303 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag); in pm8001_chip_sata_req()
4307 pm8001_ccb_task_free_done(pm8001_ha, task, in pm8001_chip_sata_req()
4314 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, in pm8001_chip_sata_req()
4325 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id) in pm8001_chip_phy_start_req() argument
4332 circularQ = &pm8001_ha->inbnd_q_tbl[0]; in pm8001_chip_phy_start_req()
4347 pm8001_ha->sas_addr, SAS_ADDR_SIZE); in pm8001_chip_phy_start_req()
4349 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, in pm8001_chip_phy_start_req()
4359 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha, in pm8001_chip_phy_stop_req() argument
4367 circularQ = &pm8001_ha->inbnd_q_tbl[0]; in pm8001_chip_phy_stop_req()
4371 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, in pm8001_chip_phy_stop_req()
4379 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha, in pm8001_chip_reg_dev_req() argument
4394 circularQ = &pm8001_ha->inbnd_q_tbl[0]; in pm8001_chip_reg_dev_req()
4397 rc = pm8001_tag_alloc(pm8001_ha, &tag); in pm8001_chip_reg_dev_req()
4400 ccb = &pm8001_ha->ccb_info[tag]; in pm8001_chip_reg_dev_req()
4431 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, in pm8001_chip_reg_dev_req()
4434 pm8001_tag_free(pm8001_ha, tag); in pm8001_chip_reg_dev_req()
4442 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha, in pm8001_chip_dereg_dev_req() argument
4450 circularQ = &pm8001_ha->inbnd_q_tbl[0]; in pm8001_chip_dereg_dev_req()
4454 pm8001_dbg(pm8001_ha, MSG, "unregister device device_id = %d\n", in pm8001_chip_dereg_dev_req()
4456 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, in pm8001_chip_dereg_dev_req()
4467 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha, in pm8001_chip_phy_ctl_req() argument
4475 circularQ = &pm8001_ha->inbnd_q_tbl[0]; in pm8001_chip_phy_ctl_req()
4479 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, in pm8001_chip_phy_ctl_req()
4484 static u32 pm8001_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha) in pm8001_chip_is_our_interrupt() argument
4491 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); in pm8001_chip_is_our_interrupt()
4504 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec) in pm8001_chip_isr() argument
4506 pm8001_chip_interrupt_disable(pm8001_ha, vec); in pm8001_chip_isr()
4507 pm8001_dbg(pm8001_ha, DEVIO, in pm8001_chip_isr()
4509 vec, pm8001_cr32(pm8001_ha, 0, 0x30)); in pm8001_chip_isr()
4510 process_oq(pm8001_ha, vec); in pm8001_chip_isr()
4511 pm8001_chip_interrupt_enable(pm8001_ha, vec); in pm8001_chip_isr()
4515 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc, in send_task_abort() argument
4521 circularQ = &pm8001_ha->inbnd_q_tbl[0]; in send_task_abort()
4533 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, in send_task_abort()
4541 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha, in pm8001_chip_abort_task() argument
4546 pm8001_dbg(pm8001_ha, EH, "cmd_tag = %x, abort task tag = 0x%x\n", in pm8001_chip_abort_task()
4555 rc = send_task_abort(pm8001_ha, opc, device_id, flag, in pm8001_chip_abort_task()
4558 pm8001_dbg(pm8001_ha, EH, "rc= %d\n", rc); in pm8001_chip_abort_task()
4568 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha, in pm8001_chip_ssp_tm_req() argument
4585 if (pm8001_ha->chip_id != chip_8001) in pm8001_chip_ssp_tm_req()
4587 circularQ = &pm8001_ha->inbnd_q_tbl[0]; in pm8001_chip_ssp_tm_req()
4588 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd, in pm8001_chip_ssp_tm_req()
4593 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha, in pm8001_chip_get_nvmd_req() argument
4612 circularQ = &pm8001_ha->inbnd_q_tbl[0]; in pm8001_chip_get_nvmd_req()
4614 rc = pm8001_tag_alloc(pm8001_ha, &tag); in pm8001_chip_get_nvmd_req()
4619 ccb = &pm8001_ha->ccb_info[tag]; in pm8001_chip_get_nvmd_req()
4634 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); in pm8001_chip_get_nvmd_req()
4636 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); in pm8001_chip_get_nvmd_req()
4643 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); in pm8001_chip_get_nvmd_req()
4645 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); in pm8001_chip_get_nvmd_req()
4652 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); in pm8001_chip_get_nvmd_req()
4654 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); in pm8001_chip_get_nvmd_req()
4661 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); in pm8001_chip_get_nvmd_req()
4663 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); in pm8001_chip_get_nvmd_req()
4671 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); in pm8001_chip_get_nvmd_req()
4673 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); in pm8001_chip_get_nvmd_req()
4679 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, in pm8001_chip_get_nvmd_req()
4683 pm8001_tag_free(pm8001_ha, tag); in pm8001_chip_get_nvmd_req()
4688 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha, in pm8001_chip_set_nvmd_req() argument
4705 circularQ = &pm8001_ha->inbnd_q_tbl[0]; in pm8001_chip_set_nvmd_req()
4706 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr, in pm8001_chip_set_nvmd_req()
4710 rc = pm8001_tag_alloc(pm8001_ha, &tag); in pm8001_chip_set_nvmd_req()
4715 ccb = &pm8001_ha->ccb_info[tag]; in pm8001_chip_set_nvmd_req()
4729 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); in pm8001_chip_set_nvmd_req()
4731 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); in pm8001_chip_set_nvmd_req()
4739 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); in pm8001_chip_set_nvmd_req()
4741 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); in pm8001_chip_set_nvmd_req()
4748 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); in pm8001_chip_set_nvmd_req()
4750 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); in pm8001_chip_set_nvmd_req()
4757 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi); in pm8001_chip_set_nvmd_req()
4759 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo); in pm8001_chip_set_nvmd_req()
4764 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, in pm8001_chip_set_nvmd_req()
4768 pm8001_tag_free(pm8001_ha, tag); in pm8001_chip_set_nvmd_req()
4780 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha, in pm8001_chip_fw_flash_update_build() argument
4790 circularQ = &pm8001_ha->inbnd_q_tbl[0]; in pm8001_chip_fw_flash_update_build()
4801 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, in pm8001_chip_fw_flash_update_build()
4807 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha, in pm8001_chip_fw_flash_update_req() argument
4816 void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr; in pm8001_chip_fw_flash_update_req()
4817 dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr; in pm8001_chip_fw_flash_update_req()
4824 pm8001_dbg(pm8001_ha, DEVIO, in pm8001_chip_fw_flash_update_req()
4838 rc = pm8001_tag_alloc(pm8001_ha, &tag); in pm8001_chip_fw_flash_update_req()
4843 ccb = &pm8001_ha->ccb_info[tag]; in pm8001_chip_fw_flash_update_req()
4846 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info, in pm8001_chip_fw_flash_update_req()
4850 pm8001_tag_free(pm8001_ha, tag); in pm8001_chip_fw_flash_update_req()
4865 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; in pm8001_get_gsm_dump() local
4868 gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset; in pm8001_get_gsm_dump()
4875 if (pm8001_ha->chip_id == chip_8001) in pm8001_get_gsm_dump()
4889 if (pm8001_ha->chip_id == chip_8001) in pm8001_get_gsm_dump()
4897 if (pm8001_ha->chip_id == chip_8001) { in pm8001_get_gsm_dump()
4899 if (-1 == pm8001_bar4_shift(pm8001_ha, in pm8001_get_gsm_dump()
4904 if (-1 == pm80xx_bar4_shift(pm8001_ha, in pm8001_get_gsm_dump()
4913 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & in pm8001_get_gsm_dump()
4919 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & in pm8001_get_gsm_dump()
4925 if (-1 == pm8001_bar4_shift(pm8001_ha, 0)) in pm8001_get_gsm_dump()
4927 pm8001_ha->fatal_forensic_shift_offset += 1024; in pm8001_get_gsm_dump()
4929 if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000) in pm8001_get_gsm_dump()
4930 pm8001_ha->fatal_forensic_shift_offset = 0; in pm8001_get_gsm_dump()
4935 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha, in pm8001_chip_set_dev_state_req() argument
4945 rc = pm8001_tag_alloc(pm8001_ha, &tag); in pm8001_chip_set_dev_state_req()
4948 ccb = &pm8001_ha->ccb_info[tag]; in pm8001_chip_set_dev_state_req()
4951 circularQ = &pm8001_ha->inbnd_q_tbl[0]; in pm8001_chip_set_dev_state_req()
4955 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, in pm8001_chip_set_dev_state_req()
4958 pm8001_tag_free(pm8001_ha, tag); in pm8001_chip_set_dev_state_req()
4965 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha) in pm8001_chip_sas_re_initialization() argument
4974 rc = pm8001_tag_alloc(pm8001_ha, &tag); in pm8001_chip_sas_re_initialization()
4977 ccb = &pm8001_ha->ccb_info[tag]; in pm8001_chip_sas_re_initialization()
4979 circularQ = &pm8001_ha->inbnd_q_tbl[0]; in pm8001_chip_sas_re_initialization()
4984 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, in pm8001_chip_sas_re_initialization()
4987 pm8001_tag_free(pm8001_ha, tag); in pm8001_chip_sas_re_initialization()