Lines Matching refs:pm8001_cr32
399 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW); in pm8001_bar4_shift()
470 value = pm8001_cr32(pm8001_ha, 2, 0xd8); in mpi_set_phys_g3_with_ssc()
542 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); in mpi_init_check()
570 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); in check_fw_ready()
571 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); in check_fw_ready()
575 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); in check_fw_ready()
582 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); in check_fw_ready()
590 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); in check_fw_ready()
606 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) in check_fw_ready()
608 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) in check_fw_ready()
624 value = pm8001_cr32(pm8001_ha, 0, 0x44); in init_pci_device_addresses()
633 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18); in init_pci_device_addresses()
635 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C); in init_pci_device_addresses()
637 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20); in init_pci_device_addresses()
723 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); in mpi_uninit_check()
765 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) in soft_reset_ready_check()
785 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) & in soft_reset_ready_check()
788 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); in soft_reset_ready_check()
789 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); in soft_reset_ready_check()
794 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)); in soft_reset_ready_check()
797 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)); in soft_reset_ready_check()
836 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP); in pm8001_chip_soft_rst()
847 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1); in pm8001_chip_soft_rst()
852 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE); in pm8001_chip_soft_rst()
857 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT); in pm8001_chip_soft_rst()
862 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE); in pm8001_chip_soft_rst()
867 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT); in pm8001_chip_soft_rst()
872 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) in pm8001_chip_soft_rst()
890 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); in pm8001_chip_soft_rst()
893 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); in pm8001_chip_soft_rst()
907 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); in pm8001_chip_soft_rst()
911 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); in pm8001_chip_soft_rst()
918 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)); in pm8001_chip_soft_rst()
921 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); in pm8001_chip_soft_rst()
928 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)); in pm8001_chip_soft_rst()
931 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); in pm8001_chip_soft_rst()
937 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)); in pm8001_chip_soft_rst()
948 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET); in pm8001_chip_soft_rst()
963 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); in pm8001_chip_soft_rst()
970 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); in pm8001_chip_soft_rst()
980 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); in pm8001_chip_soft_rst()
1000 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); in pm8001_chip_soft_rst()
1001 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET); in pm8001_chip_soft_rst()
1013 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)); in pm8001_chip_soft_rst()
1016 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK); in pm8001_chip_soft_rst()
1023 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)); in pm8001_chip_soft_rst()
1025 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK); in pm8001_chip_soft_rst()
1029 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)); in pm8001_chip_soft_rst()
1031 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK); in pm8001_chip_soft_rst()
1035 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)); in pm8001_chip_soft_rst()
1045 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET); in pm8001_chip_soft_rst()
1058 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & in pm8001_chip_soft_rst()
1063 regVal = pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1069 pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1073 pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1077 pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1091 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); in pm8001_chip_soft_rst()
1096 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); in pm8001_chip_soft_rst()
1103 pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1107 pm8001_cr32(pm8001_ha, 0, in pm8001_chip_soft_rst()
1127 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); in pm8001_hw_chip_rst()
1135 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET); in pm8001_hw_chip_rst()
4491 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); in pm8001_chip_is_our_interrupt()
4509 vec, pm8001_cr32(pm8001_ha, 0, 0x30)); in pm8001_chip_isr()
4913 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & in pm8001_get_gsm_dump()
4919 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) & in pm8001_get_gsm_dump()