Lines Matching +full:0 +full:x00000001
35 * #define example_bit_field_MASK 0x03
46 * bf_set(example_bit_field, &t1, 0);
70 #define lpfc_sli_intf_valid_MASK 0x00000007
74 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
76 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0
78 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
80 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0
84 #define lpfc_sli_intf_if_type_MASK 0x0000000F
86 #define LPFC_SLI_INTF_IF_TYPE_0 0
91 #define lpfc_sli_intf_sli_family_MASK 0x0000000F
93 #define LPFC_SLI_INTF_FAMILY_BE2 0x0
94 #define LPFC_SLI_INTF_FAMILY_BE3 0x1
95 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa
96 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb
98 #define lpfc_sli_intf_slirev_MASK 0x0000000F
102 #define lpfc_sli_intf_func_type_SHIFT 0
103 #define lpfc_sli_intf_func_type_MASK 0x00000001
105 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0
122 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */
132 #define LPFC_MBX_ERROR_RANGE 0x4000
133 #define LPFC_BMBX_BIT1_ADDR_HI 0x2
134 #define LPFC_BMBX_BIT1_ADDR_LO 0
137 #define LPFC_RPI_ALLOC_ERROR 0xFFFF
139 #define LPFC_ENTIRE_FCF_DATABASE 0
140 #define LPFC_DFLT_FCF_INDEX 0
143 #define LPFC_VF0 0
177 #define LPFC_PCI_FUNC0 0
184 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414
185 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001
186 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002
187 #define LPFC_CTL_PDEV_CTL_DD 0x00000004
188 #define LPFC_CTL_PDEV_CTL_LC 0x00000008
189 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00
190 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10
191 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20
192 #define LPFC_CTL_PDEV_CTL_DDL_RAS 0x1000000
200 #define LPFC_FCP_SCHED_BY_HDWQ 0
204 #define LPFC_NS_QUERY_GID_FT 0
214 #define LPFC_DEF_IMAX 0
222 #define LPFC_MIN_CPU_MAP 0
234 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
239 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
242 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */
243 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */
244 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */
245 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */
246 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */
247 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */
248 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */
260 #define lpfc_idx_rsrc_rdy_SHIFT 0
261 #define lpfc_idx_rsrc_rdy_MASK 0x00000001
265 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001
269 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001
273 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001
281 #define lpfc_abts_orig_SHIFT 0
282 #define lpfc_abts_orig_MASK 0x00000001
285 #define LPFC_ABTS_UNSOL_INT 0
287 #define lpfc_abts_rxid_SHIFT 0
288 #define lpfc_abts_rxid_MASK 0x0000FFFF
291 #define lpfc_abts_oxid_MASK 0x0000FFFF
294 #define lpfc_vndr_code_SHIFT 0
295 #define lpfc_vndr_code_MASK 0x000000FF
298 #define lpfc_rsn_expln_MASK 0x000000FF
301 #define lpfc_rsn_code_MASK 0x000000FF
312 #define lpfc_eqe_resource_id_MASK 0x0000FFFF
315 #define lpfc_eqe_minor_code_MASK 0x00000FFF
318 #define lpfc_eqe_major_code_MASK 0x00000007
320 #define lpfc_eqe_valid_SHIFT 0
321 #define lpfc_eqe_valid_MASK 0x00000001
332 #define lpfc_cqe_valid_MASK 0x00000001
335 #define lpfc_cqe_code_MASK 0x000000FF
340 #define CQE_STATUS_SUCCESS 0x0
341 #define CQE_STATUS_FCP_RSP_FAILURE 0x1
342 #define CQE_STATUS_REMOTE_STOP 0x2
343 #define CQE_STATUS_LOCAL_REJECT 0x3
344 #define CQE_STATUS_NPORT_RJT 0x4
345 #define CQE_STATUS_FABRIC_RJT 0x5
346 #define CQE_STATUS_NPORT_BSY 0x6
347 #define CQE_STATUS_FABRIC_BSY 0x7
348 #define CQE_STATUS_INTERMED_RSP 0x8
349 #define CQE_STATUS_LS_RJT 0x9
350 #define CQE_STATUS_CMD_REJECT 0xb
351 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc
352 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf
353 #define CQE_STATUS_DI_ERROR 0x16
356 #define LPFC_IOCB_STATUS_MASK 0xf
359 #define CQE_HW_STATUS_NO_ERR 0x0
360 #define CQE_HW_STATUS_UNDERRUN 0x1
361 #define CQE_HW_STATUS_OVERRUN 0x2
364 #define CQE_CODE_COMPL_WQE 0x1
365 #define CQE_CODE_RELEASE_WQE 0x2
366 #define CQE_CODE_RECEIVE 0x4
367 #define CQE_CODE_XRI_ABORTED 0x5
368 #define CQE_CODE_RECEIVE_V1 0x9
369 #define CQE_CODE_NVME_ERSP 0xd
373 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) .
375 #define WCQE_PARAM_MASK 0x1FF
381 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF
384 #define lpfc_wcqe_c_status_MASK 0x000000FF
386 #define lpfc_wcqe_c_hw_status_SHIFT 0
387 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF
389 #define lpfc_wcqe_c_ersp0_SHIFT 0
390 #define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF
395 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001
398 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001
401 #define lpfc_wcqe_c_bg_re_MASK 0x00000001
404 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001
406 #define lpfc_wcqe_c_bg_ge_SHIFT 0
407 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001
414 #define lpfc_wcqe_c_xb_MASK 0x00000001
417 #define lpfc_wcqe_c_pv_MASK 0x00000001
420 #define lpfc_wcqe_c_priority_MASK 0x00000007
425 #define lpfc_wcqe_c_sqhead_SHIFT 0
426 #define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF
436 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF
438 #define lpfc_wcqe_r_wqe_index_SHIFT 0
439 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF
453 #define lpfc_wcqe_xa_status_MASK 0x000000FF
458 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF
460 #define lpfc_wcqe_xa_xri_SHIFT 0
461 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF
468 #define lpfc_wcqe_xa_ia_MASK 0x00000001
470 #define CQE_XRI_ABORTED_IA_REMOTE 0
473 #define lpfc_wcqe_xa_br_MASK 0x00000001
475 #define CQE_XRI_ABORTED_BR_BA_ACC 0
478 #define lpfc_wcqe_xa_eo_MASK 0x00000001
480 #define CQE_XRI_ABORTED_EO_REMOTE 0
491 #define lpfc_rcqe_bindex_MASK 0x0000FFF
494 #define lpfc_rcqe_status_MASK 0x000000FF
496 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */
497 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */
498 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */
499 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */
501 #define lpfc_rcqe_fcf_id_v1_SHIFT 0
502 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F
506 #define lpfc_rcqe_length_MASK 0x0000FFFF
509 #define lpfc_rcqe_rq_id_MASK 0x000003FF
511 #define lpfc_rcqe_fcf_id_SHIFT 0
512 #define lpfc_rcqe_fcf_id_MASK 0x0000003F
514 #define lpfc_rcqe_rq_id_v1_SHIFT 0
515 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF
522 #define lpfc_rcqe_port_MASK 0x00000001
525 #define lpfc_rcqe_hdr_length_MASK 0x0000001F
531 #define lpfc_rcqe_eof_MASK 0x000000FF
533 #define FCOE_EOFn 0x41
534 #define FCOE_EOFt 0x42
535 #define FCOE_EOFni 0x49
536 #define FCOE_EOFa 0x50
537 #define lpfc_rcqe_sof_SHIFT 0
538 #define lpfc_rcqe_sof_MASK 0x000000FF
540 #define FCOE_SOFi2 0x2d
541 #define FCOE_SOFi3 0x2e
542 #define FCOE_SOFn2 0x35
543 #define FCOE_SOFn3 0x36
557 #define lpfc_bde4_last_MASK 0x00000001
559 #define lpfc_bde4_sge_offset_SHIFT 0
560 #define lpfc_bde4_sge_offset_MASK 0x000003FF
563 #define lpfc_bde4_length_SHIFT 0
564 #define lpfc_bde4_length_MASK 0x000000FF
572 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000
573 #define LPFC_PORT_SEM_MASK 0xF000
574 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
575 #define LPFC_UERR_STATUS_HI 0x00A4
576 #define LPFC_UERR_STATUS_LO 0x00A0
577 #define LPFC_UE_MASK_HI 0x00AC
578 #define LPFC_UE_MASK_LO 0x00A8
580 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
581 #define LPFC_SLI_INTF 0x0058
582 #define LPFC_SLI_ASIC_VER 0x009C
584 #define LPFC_CTL_PORT_SEM_OFFSET 0x400
586 #define lpfc_port_smphr_perr_MASK 0x1
589 #define lpfc_port_smphr_sfi_MASK 0x1
592 #define lpfc_port_smphr_nip_MASK 0x1
595 #define lpfc_port_smphr_ipc_MASK 0x1
598 #define lpfc_port_smphr_scr1_MASK 0x1
601 #define lpfc_port_smphr_scr2_MASK 0x1
604 #define lpfc_port_smphr_host_scratch_MASK 0xFF
606 #define lpfc_port_smphr_port_status_SHIFT 0
607 #define lpfc_port_smphr_port_status_MASK 0xFFFF
610 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000
611 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001
612 #define LPFC_POST_STAGE_HOST_RDY 0x0002
613 #define LPFC_POST_STAGE_BE_RESET 0x0003
614 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100
615 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101
616 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200
617 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201
618 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300
619 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301
620 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400
621 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401
622 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600
623 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601
624 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700
625 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701
626 #define LPFC_POST_STAGE_ARMFW_START 0x0800
627 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900
628 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901
629 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00
630 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01
631 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00
632 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01
633 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02
634 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03
635 #define LPFC_POST_STAGE_PARSE_XML 0x0B04
636 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05
637 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06
638 #define LPFC_POST_STAGE_RC_DONE 0x0B07
639 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08
640 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00
641 #define LPFC_POST_STAGE_PORT_READY 0xC000
642 #define LPFC_POST_STAGE_PORT_UE 0xF000
644 #define LPFC_CTL_PORT_STA_OFFSET 0x404
646 #define lpfc_sliport_status_err_MASK 0x1
649 #define lpfc_sliport_status_end_MASK 0x1
652 #define lpfc_sliport_status_oti_MASK 0x1
655 #define lpfc_sliport_status_dip_MASK 0x1
658 #define lpfc_sliport_status_rn_MASK 0x1
661 #define lpfc_sliport_status_rdy_MASK 0x1
665 #define LPFC_CTL_PORT_CTL_OFFSET 0x408
667 #define lpfc_sliport_ctrl_end_MASK 0x1
669 #define LPFC_SLIPORT_LITTLE_ENDIAN 0
672 #define lpfc_sliport_ctrl_ip_MASK 0x1
676 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C
677 #define LPFC_CTL_PORT_ER2_OFFSET 0x410
679 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418
681 #define lpfc_sliport_eqdelay_delay_MASK 0xffff
683 #define lpfc_sliport_eqdelay_id_SHIFT 0
684 #define lpfc_sliport_eqdelay_id_MASK 0xfff
688 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
691 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC
693 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF
694 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF
696 #define LPFC_HST_ISR0 0x0C18
697 #define LPFC_HST_ISR1 0x0C1C
698 #define LPFC_HST_ISR2 0x0C20
699 #define LPFC_HST_ISR3 0x0C24
700 #define LPFC_HST_ISR4 0x0C28
702 #define LPFC_HST_IMR0 0x0C48
703 #define LPFC_HST_IMR1 0x0C4C
704 #define LPFC_HST_IMR2 0x0C50
705 #define LPFC_HST_IMR3 0x0C54
706 #define LPFC_HST_IMR4 0x0C58
708 #define LPFC_HST_ISCR0 0x0C78
709 #define LPFC_HST_ISCR1 0x0C7C
710 #define LPFC_HST_ISCR2 0x0C80
711 #define LPFC_HST_ISCR3 0x0C84
712 #define LPFC_HST_ISCR4 0x0C88
750 * value. For UCNA ports running SLI4 and if_type 0, they reside in
756 #define LPFC_ULP0_RQ_DOORBELL 0x00A0
757 #define LPFC_ULP1_RQ_DOORBELL 0x00C0
758 #define LPFC_IF6_RQ_DOORBELL 0x0080
760 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF
763 #define lpfc_rq_db_list_fm_index_MASK 0x00FF
765 #define lpfc_rq_db_list_fm_id_SHIFT 0
766 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF
769 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF
771 #define lpfc_rq_db_ring_fm_id_SHIFT 0
772 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF
775 #define LPFC_ULP0_WQ_DOORBELL 0x0040
776 #define LPFC_ULP1_WQ_DOORBELL 0x0060
778 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF
781 #define lpfc_wq_db_list_fm_index_MASK 0x00FF
783 #define lpfc_wq_db_list_fm_id_SHIFT 0
784 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF
787 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF
789 #define lpfc_wq_db_ring_fm_id_SHIFT 0
790 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF
793 #define LPFC_IF6_WQ_DOORBELL 0x0040
795 #define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF
798 #define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001
801 #define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F
803 #define lpfc_if6_wq_db_list_fm_id_SHIFT 0
804 #define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF
807 #define LPFC_EQCQ_DOORBELL 0x0120
809 #define lpfc_eqcq_doorbell_se_MASK 0x0001
811 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0
814 #define lpfc_eqcq_doorbell_arm_MASK 0x0001
817 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF
820 #define lpfc_eqcq_doorbell_qt_MASK 0x0001
822 #define LPFC_QUEUE_TYPE_COMPLETION 0
825 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001
827 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0
828 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF
831 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F
833 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0
834 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF
837 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F
842 #define LPFC_IF6_CQ_DOORBELL 0x00C0
844 #define lpfc_if6_cq_doorbell_se_MASK 0x0001
846 #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0
849 #define lpfc_if6_cq_doorbell_arm_MASK 0x0001
852 #define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF
854 #define lpfc_if6_cq_doorbell_cqid_SHIFT 0
855 #define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF
858 #define LPFC_IF6_EQ_DOORBELL 0x0120
860 #define lpfc_if6_eq_doorbell_io_MASK 0x0001
862 #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0
865 #define lpfc_if6_eq_doorbell_arm_MASK 0x0001
868 #define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF
870 #define lpfc_if6_eq_doorbell_eqid_SHIFT 0
871 #define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF
874 #define LPFC_BMBX 0x0160
876 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF
879 #define lpfc_bmbx_hi_MASK 0x0001
881 #define lpfc_bmbx_rdy_SHIFT 0
882 #define lpfc_bmbx_rdy_MASK 0x0001
885 #define LPFC_MQ_DOORBELL 0x0140
886 #define LPFC_IF6_MQ_DOORBELL 0x0160
888 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF
890 #define lpfc_mq_doorbell_id_SHIFT 0
891 #define lpfc_mq_doorbell_id_MASK 0xFFFF
896 #define lpfc_mbox_hdr_emb_SHIFT 0
897 #define lpfc_mbox_hdr_emb_MASK 0x00000001
900 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F
911 #define lpfc_mbox_hdr_opcode_SHIFT 0
912 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
915 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
918 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF
921 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
926 #define lpfc_mbox_hdr_version_SHIFT 0
927 #define lpfc_mbox_hdr_version_MASK 0x000000FF
930 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF
933 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF
937 #define LPFC_Q_CREATE_VERSION_0 0
938 #define LPFC_OPCODE_VERSION_0 0
943 #define lpfc_mbox_hdr_opcode_SHIFT 0
944 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
947 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
950 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
953 #define lpfc_mbox_hdr_status_SHIFT 0
954 #define lpfc_mbox_hdr_status_MASK 0x000000FF
957 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF
976 #define LPFC_EXTENT_LOCAL 0
977 #define LPFC_TIMEOUT_DEFAULT 0
978 #define LPFC_EXTENT_VERSION_DEFAULT 0
981 #define LPFC_MBOX_SUBSYSTEM_NA 0x0
982 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1
983 #define LPFC_MBOX_SUBSYSTEM_LOWLEVEL 0xB
984 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC
989 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF
990 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF
993 #define LPFC_MBOX_OPCODE_NA 0x00
994 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C
995 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D
996 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15
997 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20
998 #define LPFC_MBOX_OPCODE_NOP 0x21
999 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29
1000 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35
1001 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36
1002 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37
1003 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A
1004 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D
1005 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E
1006 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43
1007 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45
1008 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46
1009 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D
1010 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A
1011 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B
1012 #define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D
1013 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73
1014 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74
1015 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A
1016 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B
1017 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C
1018 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D
1019 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0
1020 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1
1021 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4
1022 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5
1023 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6
1024 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8
1025 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9
1026 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB
1027 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC
1028 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD
1029 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE
1030 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5
1031 #define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF
1034 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01
1035 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02
1036 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03
1037 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04
1038 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05
1039 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06
1040 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08
1041 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09
1042 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A
1043 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B
1044 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10
1045 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D
1046 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21
1047 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22
1048 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23
1049 #define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE 0x42
1052 #define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION 0x37
1058 #define lpfc_eq_context_size_MASK 0x00000001
1060 #define LPFC_EQE_SIZE_4 0x0
1061 #define LPFC_EQE_SIZE_16 0x1
1063 #define lpfc_eq_context_valid_MASK 0x00000001
1066 #define lpfc_eq_context_autovalid_MASK 0x00000001
1070 #define lpfc_eq_context_count_MASK 0x00000003
1072 #define LPFC_EQ_CNT_256 0x0
1073 #define LPFC_EQ_CNT_512 0x1
1074 #define LPFC_EQ_CNT_1024 0x2
1075 #define LPFC_EQ_CNT_2048 0x3
1076 #define LPFC_EQ_CNT_4096 0x4
1079 #define lpfc_eq_context_delay_multi_MASK 0x000003FF
1101 #define lpfc_post_sgl_pages_xri_SHIFT 0
1102 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF
1105 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
1138 #define lpfc_mbx_eq_create_num_pages_SHIFT 0
1139 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF
1146 #define lpfc_mbx_eq_create_q_id_SHIFT 0
1147 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF
1171 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0
1172 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF
1193 #define lpfc_fwlog_enable_SHIFT 0
1194 #define lpfc_fwlog_enable_MASK 0x00000001
1197 #define lpfc_fwlog_loglvl_MASK 0x0000000F
1200 #define lpfc_fwlog_ra_WORD 0x00000008
1202 #define lpfc_fwlog_buffcnt_MASK 0x000000FF
1205 #define lpfc_fwlog_buffsz_MASK 0x000000FF
1208 #define lpfc_fwlog_acqe_SHIFT 0
1209 #define lpfc_fwlog_acqe_MASK 0x0000FFFF
1212 #define lpfc_fwlog_cqid_MASK 0x0000FFFF
1228 #define lpfc_cq_context_event_MASK 0x00000001
1231 #define lpfc_cq_context_valid_MASK 0x00000001
1234 #define lpfc_cq_context_count_MASK 0x00000003
1236 #define LPFC_CQ_CNT_256 0x0
1237 #define LPFC_CQ_CNT_512 0x1
1238 #define LPFC_CQ_CNT_1024 0x2
1239 #define LPFC_CQ_CNT_WORD7 0x3
1241 #define lpfc_cq_context_autovalid_MASK 0x00000001
1244 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */
1245 #define lpfc_cq_eq_id_MASK 0x000000FF
1247 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */
1248 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF
1260 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF
1262 #define lpfc_mbx_cq_create_num_pages_SHIFT 0
1263 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF
1270 #define lpfc_mbx_cq_create_q_id_SHIFT 0
1271 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF
1283 #define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF
1285 #define lpfc_mbx_cq_create_set_num_pages_SHIFT 0
1286 #define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF
1290 #define lpfc_mbx_cq_create_set_evt_MASK 0x00000001
1293 #define lpfc_mbx_cq_create_set_valid_MASK 0x00000001
1296 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003
1299 #define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003
1302 #define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001
1305 #define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001
1308 #define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003
1312 #define lpfc_mbx_cq_create_set_arm_MASK 0x00000001
1315 #define lpfc_mbx_cq_create_set_cq_cnt_MASK 0x00007FFF
1317 #define lpfc_mbx_cq_create_set_num_cq_SHIFT 0
1318 #define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF
1322 #define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF
1324 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0
1325 #define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF
1329 #define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF
1331 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0
1332 #define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF
1336 #define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF
1338 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0
1339 #define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF
1343 #define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF
1345 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0
1346 #define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF
1350 #define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF
1352 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0
1353 #define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF
1357 #define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF
1359 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0
1360 #define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF
1364 #define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF
1366 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0
1367 #define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF
1371 #define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF
1373 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0
1374 #define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF
1381 #define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF
1383 #define lpfc_mbx_cq_create_set_base_id_SHIFT 0
1384 #define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF
1395 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0
1396 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF
1415 struct { /* Version 0 Request */
1417 #define lpfc_mbx_wq_create_num_pages_SHIFT 0
1418 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF
1421 #define lpfc_mbx_wq_create_dua_MASK 0x00000001
1424 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF
1428 #define lpfc_mbx_wq_create_bua_SHIFT 0
1429 #define lpfc_mbx_wq_create_bua_MASK 0x00000001
1432 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF
1436 uint32_t word0; /* Word 0 is the same as in v0 */
1438 #define lpfc_mbx_wq_create_page_size_SHIFT 0
1439 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF
1441 #define LPFC_WQ_PAGE_SIZE_4096 0x1
1443 #define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001
1446 #define lpfc_mbx_wq_create_doe_MASK 0x00000001
1449 #define lpfc_mbx_wq_create_toe_MASK 0x00000001
1452 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F
1454 #define LPFC_WQ_WQE_SIZE_64 0x5
1455 #define LPFC_WQ_WQE_SIZE_128 0x6
1457 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF
1464 #define lpfc_mbx_wq_create_q_id_SHIFT 0
1465 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF
1469 #define lpfc_mbx_wq_create_bar_set_SHIFT 0
1470 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF
1472 #define WQ_PCI_BAR_0_AND_1 0x00
1473 #define WQ_PCI_BAR_2_AND_3 0x01
1474 #define WQ_PCI_BAR_4_AND_5 0x02
1476 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF
1482 #define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001
1484 #define lpfc_mbx_wq_create_v1_q_id_SHIFT 0
1485 #define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF
1488 #define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0
1489 #define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F
1494 #define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F
1496 #define lpfc_mbx_wq_create_dpp_bar_SHIFT 0
1497 #define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F
1509 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0
1510 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF
1524 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */
1525 #define lpfc_rq_context_rqe_count_MASK 0x0000000F
1532 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF
1535 #define lpfc_rq_context_rqe_size_MASK 0x0000000F
1542 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */
1543 #define lpfc_rq_context_page_size_MASK 0x000000FF
1545 #define LPFC_RQ_PAGE_SIZE_4096 0x1
1548 #define lpfc_rq_context_data_size_MASK 0x0000FFFF
1550 #define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */
1551 #define lpfc_rq_context_hdr_size_MASK 0x0000FFFF
1555 #define lpfc_rq_context_cq_id_MASK 0x000003FF
1557 #define lpfc_rq_context_buf_size_SHIFT 0
1558 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF
1560 #define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */
1561 #define lpfc_rq_context_base_cq_MASK 0x0000FFFF
1571 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1572 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1575 #define lpfc_mbx_rq_create_dua_MASK 0x00000001
1578 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001
1581 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
1589 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF
1591 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1592 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1596 #define lpfc_mbx_rq_create_bar_set_SHIFT 0
1597 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
1600 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
1611 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1612 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1615 #define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF
1618 #define lpfc_mbx_rq_create_dua_MASK 0x00000001
1621 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001
1624 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
1627 #define lpfc_mbx_rq_create_dim_MASK 0x00000001
1630 #define lpfc_mbx_rq_create_dfd_MASK 0x00000001
1633 #define lpfc_mbx_rq_create_dnb_MASK 0x00000001
1641 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF
1643 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1644 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1648 #define lpfc_mbx_rq_create_bar_set_SHIFT 0
1649 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
1652 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
1663 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0
1664 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF
1675 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */
1676 #define lpfc_mq_context_cq_id_MASK 0x000003FF
1679 #define lpfc_mq_context_ring_size_MASK 0x0000000F
1681 #define LPFC_MQ_RING_SIZE_16 0x5
1682 #define LPFC_MQ_RING_SIZE_32 0x6
1683 #define LPFC_MQ_RING_SIZE_64 0x7
1684 #define LPFC_MQ_RING_SIZE_128 0x8
1687 #define lpfc_mq_context_valid_MASK 0x00000001
1698 #define lpfc_mbx_mq_create_num_pages_SHIFT 0
1699 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF
1706 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1707 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1718 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0
1719 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF
1722 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF
1726 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001
1728 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0
1729 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1
1730 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2
1731 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3
1732 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4
1734 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001
1737 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001
1740 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001
1742 #define LPFC_EVT_CODE_FC_NO_LINK 0x0
1743 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1
1744 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2
1745 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4
1746 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8
1747 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA
1748 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10
1750 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001
1757 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1758 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1762 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2
1763 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4
1764 #define LPFC_ASYNC_EVENT_GROUP5 0x20
1772 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0
1773 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF
1785 #define LPFC_RSC_TYPE_FCOE_VFI 0x20
1786 #define LPFC_RSC_TYPE_FCOE_VPI 0x21
1787 #define LPFC_RSC_TYPE_FCOE_RPI 0x22
1788 #define LPFC_RSC_TYPE_FCOE_XRI 0x23
1795 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0
1796 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF
1801 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0
1802 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF
1805 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF
1815 #define LPFC_FC_FCOE 0x00000007
1819 #define LPFC_FCOE_INI_MODE 0x00000040
1820 #define LPFC_FCOE_TGT_MODE 0x00000080
1821 #define LPFC_DUA_MODE 0x00000800
1823 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040
1824 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080
1841 #define lpfc_mbx_set_beacon_port_num_SHIFT 0
1842 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F
1845 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003
1848 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF
1851 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF
1856 #define lpfc_mbx_set_beacon_duration_v1_MASK 0x0000FFFF
1863 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0
1864 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF
1867 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF
1876 #define lpfc_mbx_set_diag_state_diag_SHIFT 0
1877 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001
1880 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001
1882 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0
1885 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F
1888 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003
1902 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0
1903 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003
1905 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0
1906 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1
1907 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2
1908 #define LPFC_DIAG_LOOPBACK_TYPE_EXTERNAL_TRUNKED 0x3
1910 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F
1913 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003
1928 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F
1931 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003
1934 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0
1935 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF
1938 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF
1941 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0
1942 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF
1945 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF
1976 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0
1977 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF
1980 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF
1985 #define lpfc_mbx_rsrc_cnt_SHIFT 0
1986 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF
2010 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0
2011 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF
2022 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0
2023 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF
2026 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF
2037 #define lpfc_sli4_sge_offset_SHIFT 0
2038 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF
2041 #define lpfc_sli4_sge_type_MASK 0x0000000F
2043 #define LPFC_SGE_TYPE_DATA 0x0
2044 #define LPFC_SGE_TYPE_DIF 0x4
2045 #define LPFC_SGE_TYPE_LSP 0x5
2046 #define LPFC_SGE_TYPE_PEDIF 0x6
2047 #define LPFC_SGE_TYPE_PESEED 0x7
2048 #define LPFC_SGE_TYPE_DISEED 0x8
2049 #define LPFC_SGE_TYPE_ENC 0x9
2050 #define LPFC_SGE_TYPE_ATM 0xA
2051 #define LPFC_SGE_TYPE_SKIP 0xC
2053 #define lpfc_sli4_sge_last_MASK 0x00000001
2080 #define lpfc_sli4_sge_dif_apptran_SHIFT 0
2081 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF
2084 #define lpfc_sli4_sge_dif_af_MASK 0x00000001
2087 #define lpfc_sli4_sge_dif_na_MASK 0x00000001
2090 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001
2093 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F
2096 #define lpfc_sli4_sge_dif_last_MASK 0x00000001
2099 #define lpfc_sli4_sge_dif_apptag_SHIFT 0
2100 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF
2103 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007
2106 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001
2109 #define lpfc_sli4_sge_dif_me_MASK 0x00000001
2112 #define lpfc_sli4_sge_dif_re_MASK 0x00000001
2115 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001
2118 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001
2121 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F
2124 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F
2134 #define lpfc_fcf_record_mac_0_SHIFT 0
2135 #define lpfc_fcf_record_mac_0_MASK 0x000000FF
2138 #define lpfc_fcf_record_mac_1_MASK 0x000000FF
2141 #define lpfc_fcf_record_mac_2_MASK 0x000000FF
2144 #define lpfc_fcf_record_mac_3_MASK 0x000000FF
2147 #define lpfc_fcf_record_mac_4_SHIFT 0
2148 #define lpfc_fcf_record_mac_4_MASK 0x000000FF
2151 #define lpfc_fcf_record_mac_5_MASK 0x000000FF
2154 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF
2157 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF
2162 #define lpfc_fcf_record_fab_name_0_SHIFT 0
2163 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF
2166 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF
2169 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF
2172 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF
2175 #define lpfc_fcf_record_fab_name_4_SHIFT 0
2176 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF
2179 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF
2182 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF
2185 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF
2188 #define lpfc_fcf_record_fc_map_0_SHIFT 0
2189 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF
2192 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF
2195 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF
2198 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001
2201 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001
2204 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001
2207 #define lpfc_fcf_record_fcf_index_SHIFT 0
2208 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF
2211 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF
2215 #define lpfc_fcf_record_switch_name_0_SHIFT 0
2216 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF
2219 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF
2222 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF
2225 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF
2228 #define lpfc_fcf_record_switch_name_4_SHIFT 0
2229 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF
2232 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF
2235 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF
2238 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF
2247 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0
2248 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF
2256 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0
2257 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF
2264 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0
2265 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF
2273 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0
2274 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF
2277 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF
2284 #define lpfc_mbx_redisc_fcf_count_SHIFT 0
2285 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF
2289 #define lpfc_mbx_redisc_fcf_index_SHIFT 0
2290 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF
2295 #define STATUS_SUCCESS 0x0
2296 #define STATUS_FAILED 0x1
2297 #define STATUS_ILLEGAL_REQUEST 0x2
2298 #define STATUS_ILLEGAL_FIELD 0x3
2299 #define STATUS_INSUFFICIENT_BUFFER 0x4
2300 #define STATUS_UNAUTHORIZED_REQUEST 0x5
2301 #define STATUS_FLASHROM_SAVE_FAILED 0x17
2302 #define STATUS_FLASHROM_RESTORE_FAILED 0x18
2303 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a
2304 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b
2305 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c
2306 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d
2307 #define STATUS_ASSERT_FAILED 0x1e
2308 #define STATUS_INVALID_SESSION 0x1f
2309 #define STATUS_INVALID_CONNECTION 0x20
2310 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21
2311 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24
2312 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25
2313 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26
2314 #define STATUS_FLASHROM_READ_FAILED 0x27
2315 #define STATUS_POLL_IOCTL_TIMEOUT 0x28
2316 #define STATUS_ERROR_ACITMAIN 0x2a
2317 #define STATUS_REBOOT_REQUIRED 0x2c
2318 #define STATUS_FCF_IN_USE 0x3a
2319 #define STATUS_FCF_TABLE_EMPTY 0x43
2325 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67
2326 #define ADD_STATUS_FW_NOT_SUPPORTED 0xEB
2327 #define ADD_STATUS_INVALID_REQUEST 0x4B
2328 #define ADD_STATUS_FW_DOWNLOAD_HW_DISABLED 0x58
2337 #define lpfc_init_vfi_vr_MASK 0x00000001
2340 #define lpfc_init_vfi_vt_MASK 0x00000001
2343 #define lpfc_init_vfi_vf_MASK 0x00000001
2346 #define lpfc_init_vfi_vp_MASK 0x00000001
2348 #define lpfc_init_vfi_vfi_SHIFT 0
2349 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF
2353 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF
2355 #define lpfc_init_vfi_fcfi_SHIFT 0
2356 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF
2360 #define lpfc_init_vfi_pri_MASK 0x00000007
2363 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF
2367 #define lpfc_init_vfi_hop_count_MASK 0x000000FF
2370 #define MBX_VFI_IN_USE 0x9F02
2376 #define lpfc_reg_vfi_upd_MASK 0x00000001
2379 #define lpfc_reg_vfi_vp_MASK 0x00000001
2381 #define lpfc_reg_vfi_vfi_SHIFT 0
2382 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF
2386 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF
2388 #define lpfc_reg_vfi_fcfi_SHIFT 0
2389 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF
2396 #define lpfc_reg_vfi_nport_id_SHIFT 0
2397 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF
2400 #define lpfc_reg_vfi_bbcr_MASK 0x00000001
2403 #define lpfc_reg_vfi_bbscn_MASK 0x0000000F
2410 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF
2412 #define lpfc_init_vpi_vpi_SHIFT 0
2413 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF
2420 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0
2421 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF
2425 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0
2426 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF
2429 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001
2432 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF
2435 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001
2438 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001
2442 #define lpfc_mbx_read_vpi_vpi_SHIFT 0
2443 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF
2446 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0
2447 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF
2450 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF
2453 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF
2456 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF
2459 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0
2460 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF
2463 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF
2466 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF
2469 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001
2476 #define lpfc_unreg_vfi_vfi_SHIFT 0
2477 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF
2483 #define lpfc_resume_rpi_index_SHIFT 0
2484 #define lpfc_resume_rpi_index_MASK 0x0000FFFF
2487 #define lpfc_resume_rpi_ii_MASK 0x00000003
2489 #define RESUME_INDEX_RPI 0
2496 #define REG_FCF_INVALID_QID 0xFFFF
2499 #define lpfc_reg_fcfi_info_index_SHIFT 0
2500 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF
2503 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF
2506 #define lpfc_reg_fcfi_rq_id1_SHIFT 0
2507 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF
2510 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF
2513 #define lpfc_reg_fcfi_rq_id3_SHIFT 0
2514 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF
2517 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF
2521 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF
2524 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF
2527 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF
2529 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0
2530 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF
2534 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF
2537 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF
2540 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF
2542 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0
2543 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF
2547 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF
2550 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF
2553 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF
2555 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0
2556 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF
2560 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF
2563 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF
2566 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF
2568 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0
2569 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF
2573 #define lpfc_reg_fcfi_mam_MASK 0x00000003
2575 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */
2579 #define lpfc_reg_fcfi_vv_MASK 0x00000001
2581 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0
2582 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF
2588 #define lpfc_reg_fcfi_mrq_info_index_SHIFT 0
2589 #define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF
2592 #define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF
2595 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0
2596 #define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF
2599 #define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF
2602 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0
2603 #define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF
2606 #define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF
2610 #define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF
2613 #define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF
2616 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF
2618 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0
2619 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF
2623 #define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF
2626 #define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF
2629 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF
2631 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0
2632 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF
2636 #define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF
2639 #define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF
2642 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF
2644 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0
2645 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF
2649 #define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF
2652 #define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF
2655 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF
2657 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0
2658 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF
2662 #define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001
2665 #define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001
2668 #define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001
2671 #define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001
2674 #define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001
2677 #define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001
2680 #define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001
2683 #define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001
2686 #define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001
2689 #define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001
2692 #define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001
2695 #define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001
2698 #define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001
2701 #define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001
2704 #define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001
2707 #define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001
2710 #define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001
2713 #define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001
2716 #define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001
2718 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0
2719 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF
2723 #define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F
2726 #define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F
2728 #define lpfc_reg_fcfi_mrq_npairs_SHIFT 0
2729 #define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF
2743 #define lpfc_unreg_fcfi_SHIFT 0
2744 #define lpfc_unreg_fcfi_MASK 0x0000FFFF
2751 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F
2754 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001
2757 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003
2759 #define LPFC_PREDCBX_CEE_MODE 0
2762 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001
2765 #define LPFC_G7_ASIC_1 0xd
2770 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0
2771 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF
2774 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF
2777 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF
2780 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF
2789 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0
2790 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF
2801 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001
2804 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0
2805 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F
2808 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003
2810 #define LPFC_LNK_TYPE_GE 0
2813 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001
2816 #define lpfc_mbx_rd_conf_trunk_MASK 0x0000000F
2819 #define lpfc_mbx_rd_conf_pt_MASK 0x00000003
2822 #define lpfc_mbx_rd_conf_tf_MASK 0x00000001
2825 #define lpfc_mbx_rd_conf_ptv_MASK 0x00000001
2828 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF
2832 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0
2833 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF
2837 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0
2838 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF
2841 #define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF
2845 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0
2846 #define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F
2849 #define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F
2852 #define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F
2855 #define lpfc_mbx_rd_conf_lmt_SHIFT 0
2856 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF
2861 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0
2862 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF
2865 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF
2868 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0
2869 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF
2872 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF
2875 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0
2876 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF
2879 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF
2882 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0
2883 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF
2886 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF
2890 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF
2893 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0
2894 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF
2897 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF
2900 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0
2901 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF
2904 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF
2910 #define lpfc_mbx_rq_ftr_qry_SHIFT 0
2911 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001
2914 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0
2915 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001
2918 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001
2921 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001
2924 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001
2927 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001
2930 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001
2933 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001
2936 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001
2939 #define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001
2942 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001
2945 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001
2948 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0
2949 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001
2952 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001
2955 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001
2958 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001
2961 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001
2964 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001
2967 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001
2970 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001
2973 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001
2976 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001
2982 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0
2983 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f
2986 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff
2989 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0
2990 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff
2993 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff
2996 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0
2997 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff
3004 #define DMP_PAGE_A0 0xa0
3005 #define DMP_PAGE_A2 0xa2
3016 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */
3017 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */
3018 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */
3019 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */
3020 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */
3021 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */
3022 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */
3023 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */
3024 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */
3025 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */
3026 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */
3027 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */
3028 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */
3029 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */
3030 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */
3031 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */
3035 #define SSF_IDENTIFIER 0
3076 #define SSF_TEMP_HIGH_ALARM 0
3201 #define cfg_prot_type_SHIFT 0
3202 #define cfg_prot_type_MASK 0x000000FF
3205 #define cfg_ft_SHIFT 0
3206 #define cfg_ft_MASK 0x00000001
3209 #define cfg_sli_rev_MASK 0x0000000f
3212 #define cfg_sli_family_MASK 0x0000000f
3215 #define cfg_if_type_MASK 0x0000000f
3218 #define cfg_sli_hint_1_MASK 0x000000ff
3221 #define cfg_sli_hint_2_MASK 0x0000001f
3225 #define cfg_eqav_MASK 0x00000001
3230 #define cfg_cqv_MASK 0x00000003
3233 #define cfg_cqpsize_MASK 0x000000ff
3236 #define cfg_cqav_MASK 0x00000001
3241 #define cfg_mqv_MASK 0x00000003
3245 #define cfg_wqpcnt_SHIFT 0
3246 #define cfg_wqpcnt_MASK 0x0000000f
3249 #define cfg_wqsize_MASK 0x0000000f
3252 #define cfg_wqv_MASK 0x00000003
3255 #define cfg_wqpsize_MASK 0x000000ff
3260 #define cfg_rqv_MASK 0x00000003
3264 #define cfg_rq_db_window_MASK 0x0000000f
3267 #define cfg_fcoe_SHIFT 0
3268 #define cfg_fcoe_MASK 0x00000001
3271 #define cfg_ext_MASK 0x00000001
3274 #define cfg_hdrr_MASK 0x00000001
3277 #define cfg_phwq_MASK 0x00000001
3280 #define cfg_oas_MASK 0x00000001
3283 #define cfg_loopbk_scope_MASK 0x0000000f
3287 #define cfg_sgl_page_cnt_SHIFT 0
3288 #define cfg_sgl_page_cnt_MASK 0x0000000f
3291 #define cfg_sgl_page_size_MASK 0x000000ff
3294 #define cfg_sgl_pp_align_MASK 0x000000ff
3301 #define cfg_ext_embed_cb_SHIFT 0
3302 #define cfg_ext_embed_cb_MASK 0x00000001
3305 #define cfg_mds_diags_MASK 0x00000001
3308 #define cfg_nvme_MASK 0x00000001
3311 #define cfg_xib_MASK 0x00000001
3314 #define cfg_xpsgl_MASK 0x00000001
3317 #define cfg_eqdr_MASK 0x00000001
3320 #define cfg_nosr_MASK 0x00000001
3324 #define cfg_bv1s_MASK 0x00000001
3327 #define cfg_pvl_MASK 0x00000001
3331 #define cfg_nsler_MASK 0x00000001
3335 #define cfg_max_tow_xri_SHIFT 0
3336 #define cfg_max_tow_xri_MASK 0x0000ffff
3344 #define cfg_frag_field_offset_SHIFT 0
3345 #define cfg_frag_field_offset_MASK 0x0000ffff
3349 #define cfg_frag_field_size_MASK 0x0000ffff
3353 #define cfg_sgl_field_offset_SHIFT 0
3354 #define cfg_sgl_field_offset_MASK 0x0000ffff
3358 #define cfg_sgl_field_size_MASK 0x0000ffff
3366 #define LPFC_SET_UE_RECOVERY 0x10
3367 #define LPFC_SET_MDS_DIAGS 0x12
3368 #define LPFC_SET_DUAL_DUMP 0x1e
3374 #define lpfc_mbx_set_feature_UER_SHIFT 0
3375 #define lpfc_mbx_set_feature_UER_MASK 0x00000001
3378 #define lpfc_mbx_set_feature_mds_MASK 0x00000001
3381 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001
3383 #define lpfc_mbx_set_feature_dd_SHIFT 0
3384 #define lpfc_mbx_set_feature_dd_MASK 0x00000001
3387 #define lpfc_mbx_set_feature_ddquery_MASK 0x00000001
3389 #define LPFC_DISABLE_DUAL_DUMP 0
3393 #define lpfc_mbx_set_feature_UERP_SHIFT 0
3394 #define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff
3397 #define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff
3402 #define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2
3415 #define lpfc_mbx_set_trunk_mode_SHIFT 0
3416 #define lpfc_mbx_set_trunk_mode_MASK 0xFF
3433 #define lpfc_rsrc_desc_pcie_type_SHIFT 0
3434 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff
3436 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40
3438 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff
3441 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0
3442 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff
3446 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0
3447 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff
3450 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff
3453 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff
3456 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0
3457 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff
3463 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0
3464 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff
3466 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43
3468 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff
3470 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0
3474 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0
3475 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff
3478 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff
3481 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0
3482 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff
3485 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff
3488 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0
3489 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff
3492 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff
3495 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0
3496 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff
3499 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff
3502 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0
3503 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff
3506 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff
3516 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0
3517 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f
3520 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003
3523 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001
3526 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001
3529 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff
3547 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
3548 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
3549 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
3561 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
3562 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
3563 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
3567 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0
3568 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff
3571 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003
3585 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0
3586 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff
3589 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff
3606 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0
3607 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff
3610 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff
3613 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff
3617 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0
3618 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff
3621 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff
3624 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff
3627 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0
3628 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff
3631 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff
3634 #define lpfc_cntl_attr_cache_valid_SHIFT 0
3635 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff
3638 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff
3641 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff
3644 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f
3647 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003
3654 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0
3655 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff
3658 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff
3661 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0
3662 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff
3665 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff
3668 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0
3669 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff
3672 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff
3675 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff
3678 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff
3682 #define lpfc_cntl_attr_num_netfil_SHIFT 0
3683 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff
3698 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0
3699 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003
3704 #define lpfc_mbx_get_port_name_name0_SHIFT 0
3705 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF
3708 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF
3711 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF
3714 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF
3716 #define LPFC_LINK_NUMBER_0 0
3725 #define MB_CQE_STATUS_SUCCESS 0x0
3726 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1
3727 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2
3728 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3
3729 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4
3730 #define MB_CQE_STATUS_DMA_FAILED 0x5
3739 #define lpfc_wr_object_eof_MASK 0x00000001
3742 #define lpfc_wr_object_eas_MASK 0x00000001
3744 #define lpfc_wr_object_write_length_SHIFT 0
3745 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF
3755 #define lpfc_wr_object_change_status_SHIFT 0
3756 #define lpfc_wr_object_change_status_MASK 0x000000FF
3758 #define LPFC_CHANGE_STATUS_NO_RESET_NEEDED 0x00
3759 #define LPFC_CHANGE_STATUS_PHYS_DEV_RESET 0x01
3760 #define LPFC_CHANGE_STATUS_FW_RESET 0x02
3761 #define LPFC_CHANGE_STATUS_PORT_MIGRATION 0x04
3762 #define LPFC_CHANGE_STATUS_PCI_RESET 0x05
3764 #define lpfc_wr_object_csf_MASK 0x00000001
3774 #define lpfc_mqe_status_MASK 0x0000FFFF
3777 #define lpfc_mqe_command_MASK 0x000000FF
3840 #define lpfc_mcqe_status_SHIFT 0
3841 #define lpfc_mcqe_status_MASK 0x0000FFFF
3844 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF
3850 #define lpfc_trailer_valid_MASK 0x00000001
3853 #define lpfc_trailer_async_MASK 0x00000001
3856 #define lpfc_trailer_hpi_MASK 0x00000001
3859 #define lpfc_trailer_completed_MASK 0x00000001
3862 #define lpfc_trailer_consumed_MASK 0x00000001
3865 #define lpfc_trailer_type_MASK 0x000000FF
3868 #define lpfc_trailer_code_MASK 0x000000FF
3870 #define LPFC_TRAILER_CODE_LINK 0x1
3871 #define LPFC_TRAILER_CODE_FCOE 0x2
3872 #define LPFC_TRAILER_CODE_DCBX 0x3
3873 #define LPFC_TRAILER_CODE_GRP5 0x5
3874 #define LPFC_TRAILER_CODE_FC 0x10
3875 #define LPFC_TRAILER_CODE_SLI 0x11
3881 #define lpfc_acqe_link_speed_MASK 0x000000FF
3883 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0
3884 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1
3885 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2
3886 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3
3887 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4
3888 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5
3889 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6
3890 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7
3891 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8
3893 #define lpfc_acqe_link_duplex_MASK 0x000000FF
3895 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0
3896 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1
3897 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2
3899 #define lpfc_acqe_link_status_MASK 0x000000FF
3901 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0
3902 #define LPFC_ASYNC_LINK_STATUS_UP 0x1
3903 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2
3904 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3
3906 #define lpfc_acqe_link_type_MASK 0x00000003
3908 #define lpfc_acqe_link_number_SHIFT 0
3909 #define lpfc_acqe_link_number_MASK 0x0000003F
3912 #define lpfc_acqe_link_fault_SHIFT 0
3913 #define lpfc_acqe_link_fault_MASK 0x000000FF
3915 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0
3916 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1
3917 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2
3918 #define LPFC_ASYNC_LINK_FAULT_LR_LRR 0x3
3920 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF
3924 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0
3925 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1
3931 #define lpfc_acqe_fip_fcf_count_SHIFT 0
3932 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF
3935 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF
3939 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1
3940 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2
3941 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3
3942 #define LPFC_FIP_EVENT_TYPE_CVL 0x4
3943 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5
3956 #define lpfc_acqe_grp5_type_MASK 0x00000003
3958 #define lpfc_acqe_grp5_number_SHIFT 0
3959 #define lpfc_acqe_grp5_number_MASK 0x0000003F
3963 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF
3974 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF
3976 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0
3977 #define LPFC_FC_LA_SPEED_1G 0x1
3978 #define LPFC_FC_LA_SPEED_2G 0x2
3979 #define LPFC_FC_LA_SPEED_4G 0x4
3980 #define LPFC_FC_LA_SPEED_8G 0x8
3981 #define LPFC_FC_LA_SPEED_10G 0xA
3982 #define LPFC_FC_LA_SPEED_16G 0x10
3983 #define LPFC_FC_LA_SPEED_32G 0x20
3984 #define LPFC_FC_LA_SPEED_64G 0x21
3985 #define LPFC_FC_LA_SPEED_128G 0x22
3986 #define LPFC_FC_LA_SPEED_256G 0x23
3988 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF
3990 #define LPFC_FC_LA_TOP_UNKOWN 0x0
3991 #define LPFC_FC_LA_TOP_P2P 0x1
3992 #define LPFC_FC_LA_TOP_FCAL 0x2
3993 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3
3994 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4
3996 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF
3998 #define LPFC_FC_LA_TYPE_LINK_UP 0x1
3999 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2
4000 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3
4001 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4
4002 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5
4003 #define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6
4004 #define LPFC_FC_LA_TYPE_TRUNKING_EVENT 0x7
4006 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003
4008 #define LPFC_LINK_TYPE_ETHERNET 0x0
4009 #define LPFC_LINK_TYPE_FC 0x1
4010 #define lpfc_acqe_fc_la_port_number_SHIFT 0
4011 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F
4014 /* Attention Type is 0x07 (Trunking Event) word0 */
4016 #define lpfc_acqe_fc_la_trunk_link_status_port0_MASK 0x0000001
4019 #define lpfc_acqe_fc_la_trunk_link_status_port1_MASK 0x0000001
4022 #define lpfc_acqe_fc_la_trunk_link_status_port2_MASK 0x0000001
4025 #define lpfc_acqe_fc_la_trunk_link_status_port3_MASK 0x0000001
4028 #define lpfc_acqe_fc_la_trunk_config_port0_MASK 0x0000001
4031 #define lpfc_acqe_fc_la_trunk_config_port1_MASK 0x0000001
4034 #define lpfc_acqe_fc_la_trunk_config_port2_MASK 0x0000001
4037 #define lpfc_acqe_fc_la_trunk_config_port3_MASK 0x0000001
4041 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF
4043 #define lpfc_acqe_fc_la_fault_SHIFT 0
4044 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF
4046 #define lpfc_acqe_fc_la_trunk_fault_SHIFT 0
4047 #define lpfc_acqe_fc_la_trunk_fault_MASK 0x0000000F
4050 #define lpfc_acqe_fc_la_trunk_linkmask_MASK 0x000000F
4052 #define LPFC_FC_LA_FAULT_NONE 0x0
4053 #define LPFC_FC_LA_FAULT_LOCAL 0x1
4054 #define LPFC_FC_LA_FAULT_REMOTE 0x2
4057 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1
4058 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2
4064 #define lpfc_sli_misconfigured_port0_state_SHIFT 0
4065 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF
4068 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF
4071 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF
4074 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF
4077 #define lpfc_sli_misconfigured_port0_op_SHIFT 0
4078 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001
4081 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003
4084 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001
4087 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003
4090 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001
4093 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003
4096 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001
4099 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003
4102 #define LPFC_SLI_EVENT_STATUS_VALID 0x00
4103 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01
4104 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02
4105 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03
4106 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04
4107 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05
4115 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1
4116 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2
4117 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3
4118 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4
4119 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5
4120 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9
4121 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA
4122 #define LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN 0xF
4123 #define LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE 0x10
4140 #define NO_XRI 0xffff
4144 #define wqe_xri_tag_SHIFT 0
4145 #define wqe_xri_tag_MASK 0x0000FFFF
4148 #define wqe_ctxt_tag_MASK 0x0000FFFF
4151 #define wqe_dif_SHIFT 0
4152 #define wqe_dif_MASK 0x00000003
4158 #define wqe_ct_MASK 0x00000003
4161 #define wqe_status_MASK 0x0000000f
4164 #define wqe_cmnd_MASK 0x000000ff
4167 #define wqe_class_MASK 0x00000007
4170 #define wqe_ar_MASK 0x00000001
4176 #define wqe_pu_MASK 0x00000003
4179 #define wqe_erp_MASK 0x00000001
4185 #define wqe_lnk_MASK 0x00000001
4188 #define wqe_tmo_MASK 0x000000ff
4192 #define wqe_reqtag_SHIFT 0
4193 #define wqe_reqtag_MASK 0x0000FFFF
4196 #define wqe_temp_rpi_MASK 0x0000FFFF
4199 #define wqe_rcvoxid_MASK 0x0000FFFF
4202 #define wqe_sof_MASK 0x000000FF
4205 #define wqe_eof_MASK 0x000000FF
4208 #define wqe_ebde_cnt_SHIFT 0
4209 #define wqe_ebde_cnt_MASK 0x0000000f
4212 #define wqe_nvme_MASK 0x00000001
4215 #define wqe_oas_MASK 0x00000001
4218 #define wqe_lenloc_MASK 0x00000003
4220 #define LPFC_WQE_LENLOC_NONE 0
4225 #define wqe_qosd_MASK 0x00000001
4228 #define wqe_xbl_MASK 0x00000001
4231 #define wqe_iod_MASK 0x00000001
4233 #define LPFC_WQE_IOD_NONE 0
4234 #define LPFC_WQE_IOD_WRITE 0
4237 #define wqe_dbde_MASK 0x00000001
4240 #define wqe_wqes_MASK 0x00000001
4244 #define wqe_wqid_MASK 0x00007fff
4247 #define wqe_pri_MASK 0x00000007
4250 #define wqe_pv_MASK 0x00000001
4253 #define wqe_xc_MASK 0x00000001
4256 #define wqe_sr_MASK 0x00000001
4259 #define wqe_ccpe_MASK 0x00000001
4262 #define wqe_ccp_MASK 0x000000ff
4265 #define wqe_cmd_type_SHIFT 0
4266 #define wqe_cmd_type_MASK 0x0000000f
4269 #define wqe_els_id_MASK 0x00000003
4274 #define LPFC_ELS_ID_DEFAULT 0
4276 #define wqe_irsp_MASK 0x00000001
4279 #define wqe_pbde_MASK 0x00000001
4282 #define wqe_sup_MASK 0x00000001
4285 #define wqe_ffrq_MASK 0x00000001
4288 #define wqe_wqec_MASK 0x00000001
4291 #define wqe_irsplen_MASK 0x0000000f
4294 #define wqe_cqid_MASK 0x0000ffff
4296 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff
4301 #define wqe_els_did_SHIFT 0
4302 #define wqe_els_did_MASK 0x00FFFFFF
4305 #define wqe_xmit_bls_pt_MASK 0x00000003
4308 #define wqe_xmit_bls_ar_MASK 0x00000001
4311 #define wqe_xmit_bls_xo_MASK 0x00000001
4328 #define els_req64_sid_SHIFT 0
4329 #define els_req64_sid_MASK 0x00FFFFFF
4332 #define els_req64_sp_MASK 0x00000001
4335 #define els_req64_vf_MASK 0x00000001
4341 #define els_req64_vfid_MASK 0x00000FFF
4344 #define els_req64_pri_MASK 0x00000007
4348 #define els_req64_hopcnt_MASK 0x000000ff
4358 #define els_rsp64_sid_SHIFT 0
4359 #define els_rsp64_sid_MASK 0x00FFFFFF
4362 #define els_rsp64_sp_MASK 0x00000001
4367 #define wqe_rsp_temp_rpi_SHIFT 0
4368 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF
4377 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff
4380 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff
4383 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0
4384 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff
4387 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff
4390 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff
4393 #define xmit_bls_rsp64_rxid_SHIFT 0
4394 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff
4397 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff
4400 #define xmit_bls_rsp64_seqcnthi_SHIFT 0
4401 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff
4404 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff
4411 #define xmit_bls_rsp64_temprpi_SHIFT 0
4412 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff
4420 #define wqe_si_MASK 0x000000001
4423 #define wqe_la_MASK 0x000000001
4426 #define wqe_xo_MASK 0x000000001
4429 #define wqe_ls_MASK 0x000000001
4432 #define wqe_dfctl_MASK 0x0000000ff
4435 #define wqe_type_MASK 0x0000000ff
4438 #define wqe_rctl_MASK 0x0000000ff
4478 #define prli_acc_rsp_code_MASK 0x0000000f
4481 #define prli_estabImagePair_MASK 0x00000001
4484 #define prli_type_code_ext_MASK 0x000000ff
4487 #define prli_type_code_MASK 0x000000ff
4493 #define prli_fba_SHIFT 0
4494 #define prli_fba_MASK 0x00000001
4497 #define prli_disc_MASK 0x00000001
4500 #define prli_tgt_MASK 0x00000001
4503 #define prli_init_MASK 0x00000001
4506 #define prli_conf_MASK 0x00000001
4509 #define prli_nsler_MASK 0x00000001
4512 #define prli_fb_sz_SHIFT 0
4513 #define prli_fb_sz_MASK 0x0000ffff
4519 uint32_t rsrvd[5]; /* words 0-4 */
4532 #define abort_cmd_ia_SHIFT 0
4533 #define abort_cmd_ia_MASK 0x000000001
4536 #define abort_cmd_criteria_MASK 0x0000000ff
4548 #define cmd_buff_len_MASK 0x00000ffff
4550 #define payload_offset_len_SHIFT 0
4551 #define payload_offset_len_MASK 0x0000ffff
4564 #define cmd_buff_len_MASK 0x00000ffff
4566 #define payload_offset_len_SHIFT 0
4567 #define payload_offset_len_MASK 0x0000ffff
4577 struct ulp_bde64 bde; /* words 0-2 */
4580 #define cmd_buff_len_MASK 0x00000ffff
4582 #define payload_offset_len_SHIFT 0
4583 #define payload_offset_len_MASK 0x0000ffff
4620 #define CMD_SEND_FRAME 0xE1
4623 struct ulp_bde64 bde; /* words 0-2 */
4691 #define MAGIC_NUMBER_G6 0xFEAA0003
4692 #define MAGIC_NUMBER_G7 0xFEAA0005
4699 #define lpfc_grp_hdr_file_type_MASK 0x000000FF
4702 #define lpfc_grp_hdr_id_MASK 0x000000FF
4710 #define FCP_COMMAND 0x0
4711 #define NVME_READ_CMD 0x0
4712 #define FCP_COMMAND_DATA_OUT 0x1
4713 #define NVME_WRITE_CMD 0x1
4714 #define FCP_COMMAND_TRECEIVE 0x2
4715 #define FCP_COMMAND_TRSP 0x3
4716 #define FCP_COMMAND_TSEND 0x7
4717 #define OTHER_COMMAND 0x8
4718 #define ELS_COMMAND_NON_FIP 0xC
4719 #define ELS_COMMAND_FIP 0xD
4721 #define LPFC_NVME_EMBED_CMD 0x0
4722 #define LPFC_NVME_EMBED_WRITE 0x1
4723 #define LPFC_NVME_EMBED_READ 0x2
4726 #define CMD_ABORT_XRI_WQE 0x0F
4727 #define CMD_XMIT_SEQUENCE64_WQE 0x82
4728 #define CMD_XMIT_BCAST64_WQE 0x84
4729 #define CMD_ELS_REQUEST64_WQE 0x8A
4730 #define CMD_XMIT_ELS_RSP64_WQE 0x95
4731 #define CMD_XMIT_BLS_RSP64_WQE 0x97
4732 #define CMD_FCP_IWRITE64_WQE 0x98
4733 #define CMD_FCP_IREAD64_WQE 0x9A
4734 #define CMD_FCP_ICMND64_WQE 0x9C
4735 #define CMD_FCP_TSEND64_WQE 0x9F
4736 #define CMD_FCP_TRECEIVE64_WQE 0xA1
4737 #define CMD_FCP_TRSP64_WQE 0xA3
4738 #define CMD_GEN_REQUEST64_WQE 0xC2
4740 #define CMD_WQE_MASK 0xff