Lines Matching refs:mem_ptr
2049 (unsigned long)ha->mem_ptr); in ips_host_info()
2249 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2253 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) in ips_get_bios_version()
2256 writel(1, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2260 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) in ips_get_bios_version()
2264 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2268 major = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_get_bios_version()
2271 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2274 minor = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_get_bios_version()
2277 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2280 subminor = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_get_bios_version()
4255 if (ha->mem_ptr) { in ips_free()
4258 ha->mem_ptr = NULL; in ips_free()
4501 isr = readb(ha->mem_ptr + IPS_REG_HISR); in ips_isinit_copperhead_memio()
4502 scpr = readb(ha->mem_ptr + IPS_REG_SCPR); in ips_isinit_copperhead_memio()
4530 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); in ips_isinit_morpheus()
4531 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR); in ips_isinit_morpheus()
4660 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR); in ips_enable_int_copperhead_memio()
4661 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/ in ips_enable_int_copperhead_memio()
4679 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR); in ips_enable_int_morpheus()
4681 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR); in ips_enable_int_morpheus()
4682 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/ in ips_enable_int_morpheus()
4799 Isr = readb(ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4811 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR); in ips_init_copperhead_memio()
4812 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4825 Isr = readb(ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4837 readb(ha->mem_ptr + IPS_REG_ISPR); in ips_init_copperhead_memio()
4838 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4842 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP); in ips_init_copperhead_memio()
4856 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR); in ips_init_copperhead_memio()
4859 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR); in ips_init_copperhead_memio()
4863 writel(0, ha->mem_ptr + IPS_REG_NDAE); in ips_init_copperhead_memio()
4866 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4894 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4911 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); in ips_init_morpheus()
4919 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4922 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); in ips_init_morpheus()
4939 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4950 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4967 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1); in ips_init_morpheus()
4971 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4974 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR); in ips_init_morpheus()
4976 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR); in ips_init_morpheus()
5058 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR); in ips_reset_copperhead_memio()
5063 writeb(0, ha->mem_ptr + IPS_REG_SCPR); in ips_reset_copperhead_memio()
5104 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR); in ips_reset_morpheus()
5175 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR); in ips_statinit_memio()
5177 ha->mem_ptr + IPS_REG_SQER); in ips_statinit_memio()
5178 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR); in ips_statinit_memio()
5179 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR); in ips_statinit_memio()
5234 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR); in ips_statupd_copperhead_memio()
5255 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ); in ips_statupd_morpheus()
5345 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) { in ips_issue_copperhead_memio()
5361 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR); in ips_issue_copperhead_memio()
5362 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR); in ips_issue_copperhead_memio()
5426 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ); in ips_issue_i2o_memio()
5480 Isr = readb(ha->mem_ptr + IPS_REG_HISR); in ips_isintr_copperhead_memio()
5491 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); in ips_isintr_copperhead_memio()
5513 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); in ips_isintr_morpheus()
6133 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_erase_bios_memio()
6137 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6142 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6147 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6152 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6160 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_erase_bios_memio()
6164 status = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6178 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6186 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_erase_bios_memio()
6190 status = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6214 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6219 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6339 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6343 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6347 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6355 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6359 status = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6370 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6374 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6384 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6388 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6397 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6401 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6475 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_verify_bios_memio()
6479 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) in ips_verify_bios_memio()
6482 writel(1, ha->mem_ptr + IPS_REG_FLAP); in ips_verify_bios_memio()
6485 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) in ips_verify_bios_memio()
6491 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); in ips_verify_bios_memio()
6496 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP); in ips_verify_bios_memio()
6840 char __iomem *mem_ptr; in ips_init_phase1() local
6884 mem_ptr = ioremap_ptr + offs; in ips_init_phase1()
6887 mem_ptr = NULL; in ips_init_phase1()
6907 ha->mem_ptr = mem_ptr; in ips_init_phase1()
7009 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1); in ips_init_phase1()